index
:
iCE40/yosys
master
[no description]
about
summary
refs
log
tree
commit
diff
stats
log msg
author
committer
range
path:
root
/
passes
/
pmgen
/
xilinx_dsp.cc
Commit message (
Expand
)
Author
Age
Files
Lines
*
synth_xilinx: Use opt_dff.
Marcelina Kościelnicka
2020-07-30
1
-88
/
+71
*
Use C++11 final/override keywords.
whitequark
2020-06-18
1
-2
/
+2
*
kernel: big fat patch to use more ID::*, otherwise ID(*)
Eddie Hung
2020-04-02
1
-94
/
+94
*
xilinx_dsp: Add multonly scratchpad var to bypass
David Shah
2020-02-01
1
-0
/
+7
*
xilinx_dsp: Initial DSP48A/DSP48A1 support.
Marcin Kościelnicki
2019-12-22
1
-6
/
+206
*
Merge pull request #1438 from YosysHQ/eddie/xilinx_dsp_comments
Eddie Hung
2019-10-08
1
-3
/
+11
|
\
|
*
Fix comment
Eddie Hung
2019-10-04
1
-1
/
+1
|
*
Add comments for xilinx_dsp
Eddie Hung
2019-10-04
1
-3
/
+11
*
|
Fixes for MSVC build
Miodrag Milanovic
2019-10-04
1
-0
/
+1
|
/
*
Update doc with max cascade chain of 20
Eddie Hung
2019-09-26
1
-2
/
+4
*
Do not always zero out C (e.g. during cascade breaks)
Eddie Hung
2019-09-26
1
-2
/
+0
*
Update doc
Eddie Hung
2019-09-26
1
-1
/
+2
*
xilinx_dsp_cascade to also cascade AREG and BREG
Eddie Hung
2019-09-26
1
-23
/
+19
*
Remove newline
Eddie Hung
2019-09-26
1
-1
/
+0
*
Fix memory issue since SigSpec& could be invalidated
Eddie Hung
2019-09-25
1
-6
/
+10
*
Set [AB]CASCREG to legal values
Eddie Hung
2019-09-23
1
-6
/
+10
*
Comment to explain separating CREG packing
Eddie Hung
2019-09-23
1
-0
/
+8
*
Separate out CREG packing into new pattern, to avoid conflict with PREG
Eddie Hung
2019-09-23
1
-21
/
+87
*
Use new port/param overload in pmg
Eddie Hung
2019-09-20
1
-1
/
+1
*
Output pattern matcher items as log_debug()
Eddie Hung
2019-09-20
1
-18
/
+16
*
Do not run xilinx_dsp_cascadeAB for now
Eddie Hung
2019-09-20
1
-1
/
+2
*
Run until convergence
Eddie Hung
2019-09-20
1
-3
/
+9
*
Add a xilinx_dsp_cascade matcher for PCIN -> PCOUT
Eddie Hung
2019-09-20
1
-52
/
+8
*
Clarify
Eddie Hung
2019-09-19
1
-1
/
+2
*
Fix width of D
Eddie Hung
2019-09-19
1
-1
/
+1
*
Use ID() macro
Eddie Hung
2019-09-19
1
-136
/
+136
*
Re-enable sign extension for C input
Eddie Hung
2019-09-19
1
-4
/
+4
*
Add doc on pattern detector for overflow
Eddie Hung
2019-09-18
1
-0
/
+5
*
Check overflow condition is power of 2 without using int32
Eddie Hung
2019-09-18
1
-3
/
+13
*
Add support for overflow using pattern detector
Eddie Hung
2019-09-18
1
-0
/
+19
*
Set more ports explicitly
Eddie Hung
2019-09-12
1
-0
/
+2
*
Add support for A1 and B1 registers
Eddie Hung
2019-09-11
1
-19
/
+40
*
Rename {A,B} -> {A2,B2}
Eddie Hung
2019-09-11
1
-14
/
+14
*
Add PCOUT -> PCIN non-shifted cascading
Eddie Hung
2019-09-11
1
-15
/
+22
*
Input registers to add DSP as new siguser to block upstream packing
Eddie Hung
2019-09-11
1
-8
/
+16
*
More cleanup
Eddie Hung
2019-09-11
1
-62
/
+28
*
Add support for A/B/C/D/AD reset
Eddie Hung
2019-09-11
1
-83
/
+38
*
Add support for RSTM
Eddie Hung
2019-09-11
1
-10
/
+21
*
Only pack out registers if \init is zero or x; then remove \init from PREG
Eddie Hung
2019-09-10
1
-0
/
+10
*
Fix RSTP
Eddie Hung
2019-09-10
1
-1
/
+1
*
Add support for RSTP
Eddie Hung
2019-09-10
1
-4
/
+12
*
enpol -> cepol
Eddie Hung
2019-09-10
1
-11
/
+11
*
Update help text
Eddie Hung
2019-09-10
1
-3
/
+3
*
Update xilinx_dsp help text
Eddie Hung
2019-09-10
1
-3
/
+21
*
Oops
Eddie Hung
2019-09-09
1
-0
/
+1
*
Support subtraction as well
Eddie Hung
2019-09-09
1
-112
/
+123
*
Support TWO24
Eddie Hung
2019-09-09
1
-1
/
+59
*
Refactor
Eddie Hung
2019-09-09
1
-33
/
+33
*
Add initial USE_SIMD=FOUR12 support
Eddie Hung
2019-09-09
1
-0
/
+157
*
Pack CREG
Eddie Hung
2019-09-06
1
-12
/
+41
[next]
