iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Renamed SIZE() to GetSize() because of name collision on Win32	Clifford Wolf	2014-10-10	4	-113/+113
*	sat encoding for exclusive $pmux ctrl inputs in "share" pass	Clifford Wolf	2014-10-03	1	-4/+16
*	added resource sharing of $macc cells	Clifford Wolf	2014-10-03	1	-3/+261
*	Added $_BUF_ cell type	Clifford Wolf	2014-10-03	1	-2/+2
*	remove buffers in opt_clean	Clifford Wolf	2014-10-03	1	-0/+13
*	resource sharing of $alu cells	Clifford Wolf	2014-10-03	1	-3/+21
*	Added support for "keep" on modules	Clifford Wolf	2014-09-29	2	-2/+2
*	namespace Yosys	Clifford Wolf	2014-09-27	8	-17/+45
*	Re-enabled assert for new logic loops in "share" pass	Clifford Wolf	2014-09-21	1	-4/+1
*	Various improvements regarding logic loops in "share" results	Clifford Wolf	2014-09-21	1	-37/+108
*	Logic loop bugfix for "share" pass	Clifford Wolf	2014-09-21	1	-3/+7
*	Added "share -limit"	Clifford Wolf	2014-09-21	1	-1/+13
*	Still loop bug in "share": changed assert to warning	Clifford Wolf	2014-09-21	1	-13/+25
*	Do not introduce new logic loops in "share"	Clifford Wolf	2014-09-21	1	-6/+47
*	Assert on new logic loops in "share" pass	Clifford Wolf	2014-09-21	1	-0/+48
*	Fixed wreduce $shiftx handling	Clifford Wolf	2014-09-15	1	-1/+1
*	Cleanup in wreduce	Clifford Wolf	2014-09-14	1	-11/+8
*	Corrected spelling mistakes found by lintian	Ruben Undheim	2014-09-06	1	-2/+2
*	Fixed "opt_const -fine" for $pos cells	Clifford Wolf	2014-09-04	1	-9/+4
*	Removed $bu0 cell type	Clifford Wolf	2014-09-04	3	-10/+7
*	Moved "share" and "wreduce" to passes/opt/	Clifford Wolf	2014-09-01	3	-0/+1342
*	Using std::vector<RTLIL::State> instead of RTLIL::Const for RTLIL::SigChunk::...	Clifford Wolf	2014-09-01	1	-1/+1
*	Added design->scratchpad	Clifford Wolf	2014-08-30	8	-64/+19
*	Optimize shift ops with constant rhs in opt_const	Clifford Wolf	2014-08-24	1	-0/+35
*	Added some additional log messages to opt_const	Clifford Wolf	2014-08-24	1	-1/+10
*	Renamed toposort.h to utils.h	Clifford Wolf	2014-08-17	1	-1/+1
*	Added "opt -fast"	Clifford Wolf	2014-08-16	1	-19/+45
*	Renamed $_INV_ cell type to $_NOT_	Clifford Wolf	2014-08-15	1	-6/+6
*	More idstring sort_by_* helpers and fixed tpl ordering in techmap	Clifford Wolf	2014-08-15	1	-2/+2
*	RIP $safe_pmux	Clifford Wolf	2014-08-14	3	-3/+2
*	Fixed a performance bug in opt_reduce	Clifford Wolf	2014-08-02	1	-2/+6
*	More cleanups related to RTLIL::IdString usage	Clifford Wolf	2014-08-02	4	-29/+30
*	Replaced sha1 implementation	Clifford Wolf	2014-08-01	2	-7/+1
*	Renamed port access function on RTLIL::Cell, added param access functions	Clifford Wolf	2014-07-31	5	-170/+170
*	Added $shift and $shiftx cell types (needed for correct part select behavior)	Clifford Wolf	2014-07-29	1	-7/+9
*	Using log_assert() instead of assert()	Clifford Wolf	2014-07-28	5	-7/+2
*	Added SigPool::check(bit)	Clifford Wolf	2014-07-27	1	-2/+2
*	Fixed bug in opt_clean	Clifford Wolf	2014-07-27	1	-1/+1
*	Improved performance of opt_const on large modules	Clifford Wolf	2014-07-27	1	-29/+54
*	Fixed a bug in opt_clean and some RTLIL API usage cleanups	Clifford Wolf	2014-07-27	2	-13/+14
*	Using new obj iterator API in a few places	Clifford Wolf	2014-07-27	1	-12/+11
*	Refactoring: Renamed RTLIL::Design::modules to modules_	Clifford Wolf	2014-07-27	6	-7/+7
*	Refactoring: Renamed RTLIL::Module::cells to cells_	Clifford Wolf	2014-07-27	6	-18/+18
*	Refactoring: Renamed RTLIL::Module::wires to wires_	Clifford Wolf	2014-07-27	5	-9/+9
*	Changed a lot of code to the new RTLIL::Wire constructors	Clifford Wolf	2014-07-26	1	-6/+10
*	More RTLIL::Cell API usage cleanups	Clifford Wolf	2014-07-26	1	-1/+1
*	Added RTLIL::Cell::has(portname)	Clifford Wolf	2014-07-26	1	-2/+2
*	Manual fixes for new cell connections API	Clifford Wolf	2014-07-26	4	-24/+32
*	Changed users of cell->connections_ to the new API (sed command)	Clifford Wolf	2014-07-26	6	-195/+195
*	Renamed RTLIL::{Module,Cell}::connections to connections_	Clifford Wolf	2014-07-26	6	-195/+195