Commit message (Collapse) | Author | Age | Files | Lines | |
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* | memory_share: Add -nosat and -nowiden options. | Marcelina Kościelnicka | 2021-08-14 | 1 | -7/+29 |
| | | | | This unlocks wide port recognition by default. | ||||
* | memory_share: Pass addresses through sigmap_xmux everywhere. | Marcelina Kościelnicka | 2021-08-13 | 1 | -20/+25 |
| | | | | This fixes wide port recognition in some cases. | ||||
* | kernel/mem: Introduce transparency masks. | Marcelina Kościelnicka | 2021-08-11 | 1 | -4/+7 |
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* | Refactor common parts of SAT-using optimizations into a helper. | Marcelina Kościelnicka | 2021-08-09 | 1 | -61/+10 |
| | | | | | | | | | | | | | This also aligns the functionality: - in all cases, the onehot attribute is used to create appropriate constraints (previously, opt_dff didn't do it at all, and share created one-hot constraints based on $pmux presence alone, which is unsound) - in all cases, shift and mul/div/pow cells are now skipped when importing the SAT problem (previously only memory_share did this) — this avoids creating clauses for hard cells that are unlikely to help with proving the UNSATness needed for optimization | ||||
* | memory_share: Don't skip ports with EN wired to input for SAT sharing. | Marcelina Kościelnicka | 2021-08-04 | 1 | -3/+1 |
| | | | | Fixes #2912. | ||||
* | Fixing old e-mail addresses and deadnames | Claire Xenia Wolf | 2021-06-08 | 1 | -1/+1 |
| | | | | | | | | s/((Claire|Xen|Xenia|Clifford)\s+)+(Wolf|Xen)\s+<(claire|clifford)@(symbioticeda.com|clifford.at|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi; s/((Nina|Nak|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi; s/((David)\s+)+Shah\s+<(dave|david)@(symbioticeda.com|yosyshq.com|ds0.me)>/David Shah <dave@ds0.me>/gi; s/((Miodrag)\s+)+Milanovic\s+<(miodrag|micko)@(symbioticeda.com|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi; s,https?://www.clifford.at/yosys/,http://yosyshq.net/yosys/,g; | ||||
* | memory_share: Add read port merging. | Marcelina Kościelnicka | 2021-05-29 | 1 | -0/+140 |
| | | | | | This is mostly meant for wide port recognition, but may also happen to merge some ports with compatible initial/reset values (eg. 0 vs x). | ||||
* | memory_share: Improve sat-based port sharing. | Marcelina Kościelnicka | 2021-05-28 | 1 | -117/+151 |
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* | memory_share: Improve same-address merging, recognize wide write ports. | Marcelina Kościelnicka | 2021-05-27 | 1 | -204/+77 |
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* | memory_share: Add wide port support. | Marcelina Kościelnicka | 2021-05-25 | 1 | -0/+6 |
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* | memory_share: Use Mem helpers. | Marcelina Kościelnicka | 2021-05-23 | 1 | -89/+71 |
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* | memory_share: Split off feedback path finding as a separate pass. | Marcelina Kościelnicka | 2021-05-23 | 1 | -241/+6 |
| | | | | | memory_share is actually three passes in a trenchcoat. Split off the one that has the least in common with the other two as a separate pass. | ||||
* | Use C++11 final/override keywords. | whitequark | 2020-06-18 | 1 | -2/+2 |
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* | Add flooring division operator | Xiretza | 2020-05-28 | 1 | -0/+1 |
| | | | | | | | | | | The $div and $mod cells use truncating division semantics (rounding towards 0), as defined by e.g. Verilog. Another rounding mode, flooring (rounding towards negative infinity), can be used in e.g. VHDL. The new $divfloor cell provides this flooring division. This commit also fixes the handling of $div in opt_expr, which was previously optimized as if it was $divfloor. | ||||
* | Add flooring modulo operator | Xiretza | 2020-05-28 | 1 | -0/+1 |
| | | | | | | | | | | | The $div and $mod cells use truncating division semantics (rounding towards 0), as defined by e.g. Verilog. Another rounding mode, flooring (rounding towards negative infinity), can be used in e.g. VHDL. The new $modfloor cell provides this flooring modulo (also known as "remainder" in several languages, but this name is ambiguous). This commit also fixes the handling of $mod in opt_expr, which was previously optimized as if it was $modfloor. | ||||
* | kernel: big fat patch to use more ID::*, otherwise ID(*) | Eddie Hung | 2020-04-02 | 1 | -69/+69 |
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* | kernel: use more ID::* | Eddie Hung | 2020-04-02 | 1 | -19/+19 |
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* | Merge pull request #1845 from YosysHQ/eddie/kernel_speedup | Eddie Hung | 2020-04-02 | 1 | -8/+8 |
|\ | | | | | kernel: speedup by using more pass-by-const-ref | ||||
| * | kernel: SigSpec use more const& + overloads to prevent implicit SigSpec | Eddie Hung | 2020-03-13 | 1 | -8/+8 |
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* | | memory_share: fix stray brace | Eddie Hung | 2020-03-30 | 1 | -1/+0 |
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* | | Code review fixes | Eddie Hung | 2020-03-30 | 1 | -2/+2 |
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* | | Apply suggestions from code review | Eddie Hung | 2020-03-30 | 1 | -4/+1 |
| | | | | | | Co-Authored-By: Alberto Gonzalez <61295559+boqwxp@users.noreply.github.com> | ||||
* | | kernel: share a single CellTypes within a pass | Eddie Hung | 2020-03-18 | 1 | -4/+16 |
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* | Make liberal use of IdString.in() | Eddie Hung | 2019-08-06 | 1 | -3/+3 |
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* | Consistent use of 'override' for virtual methods in derived classes. | Henner Zeller | 2018-07-20 | 1 | -2/+2 |
| | | | | | | | | | o Not all derived methods were marked 'override', but it is a great feature of C++11 that we should make use of. o While at it: touched header files got a -*- c++ -*- for emacs to provide support for that language. o use YS_OVERRIDE for all override keywords (though we should probably use the plain keyword going forward now that C++11 is established) | ||||
* | Typo fix. | Kaj Tuomi | 2016-09-08 | 1 | -1/+1 |
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* | Fixed bug in memory_share for memory ports with different ABITS | Clifford Wolf | 2016-08-22 | 1 | -0/+6 |
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* | Added "yosys -D" feature | Clifford Wolf | 2016-04-21 | 1 | -1/+1 |
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* | Bugfix and improvements in memory_share | Clifford Wolf | 2016-04-21 | 1 | -22/+19 |
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* | Renamed opt_share to opt_merge | Clifford Wolf | 2016-03-31 | 1 | -1/+1 |
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* | Import more std:: stuff into Yosys namespace | Clifford Wolf | 2015-10-25 | 1 | -1/+1 |
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* | Fixed trailing whitespaces | Clifford Wolf | 2015-07-02 | 1 | -3/+3 |
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* | Fixed memory_share for unconditional write with part select to memory | Clifford Wolf | 2015-04-22 | 1 | -0/+3 |
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* | Replaced ezDefaultSAT with ezSatPtr | Clifford Wolf | 2015-02-21 | 1 | -7/+7 |
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* | Added onehot attribute | Clifford Wolf | 2015-02-04 | 1 | -0/+13 |
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* | More dict/pool related changes | Clifford Wolf | 2014-12-27 | 1 | -2/+2 |
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* | namespace Yosys | Clifford Wolf | 2014-09-27 | 1 | -2/+2 |
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* | Corrected spelling mistakes found by lintian | Ruben Undheim | 2014-09-06 | 1 | -1/+1 |
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* | Added ModIndex helper class, some changes to RTLIL::Monitor | Clifford Wolf | 2014-08-01 | 1 | -3/+2 |
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* | Renamed modwalker.h to modtools.h | Clifford Wolf | 2014-07-31 | 1 | -5/+6 |
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* | Renamed port access function on RTLIL::Cell, added param access functions | Clifford Wolf | 2014-07-31 | 1 | -53/+53 |
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* | Added $shift and $shiftx cell types (needed for correct part select behavior) | Clifford Wolf | 2014-07-29 | 1 | -0/+2 |
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* | Refactoring: Renamed RTLIL::Design::modules to modules_ | Clifford Wolf | 2014-07-27 | 1 | -1/+1 |
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* | Refactoring: Renamed RTLIL::Module::cells to cells_ | Clifford Wolf | 2014-07-27 | 1 | -2/+2 |
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* | Refactoring: Renamed RTLIL::Module::wires to wires_ | Clifford Wolf | 2014-07-27 | 1 | -1/+1 |
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* | Manual fixes for new cell connections API | Clifford Wolf | 2014-07-26 | 1 | -13/+22 |
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* | Changed users of cell->connections_ to the new API (sed command) | Clifford Wolf | 2014-07-26 | 1 | -51/+51 |
| | | | | | | | | | git grep -l 'connections_' | xargs sed -i -r -e ' s/(->|\.)connections_\["([^"]*)"\] = (.*);/\1set("\2", \3);/g; s/(->|\.)connections_\["([^"]*)"\]/\1get("\2")/g; s/(->|\.)connections_.at\("([^"]*)"\)/\1get("\2")/g; s/(->|\.)connections_.push_back/\1connect/g; s/(->|\.)connections_/\1connections()/g;' | ||||
* | Renamed RTLIL::{Module,Cell}::connections to connections_ | Clifford Wolf | 2014-07-26 | 1 | -51/+51 |
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* | Use only module->addCell() and module->remove() to create and delete cells | Clifford Wolf | 2014-07-25 | 1 | -4/+2 |
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* | Removed RTLIL::SigSpec::optimize() | Clifford Wolf | 2014-07-23 | 1 | -2/+0 |
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