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passes
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hierarchy
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Author
Age
Files
Lines
*
Bugfix in "hierarchy -check"
Clifford Wolf
2016-11-02
1
-1
/
+1
*
Added avail params to ilang format, check module params in 'hierarchy -check'
Clifford Wolf
2016-10-22
1
-0
/
+4
*
Removed $predict again
Clifford Wolf
2016-08-28
1
-1
/
+1
*
Fixed use-after-free dict<> usage pattern in hierarchy.cc
Clifford Wolf
2016-08-16
1
-1
/
+3
*
After reading the SV spec, using non-standard predict() instead of expect()
Clifford Wolf
2016-07-21
1
-1
/
+1
*
Added basic support for $expect cells
Clifford Wolf
2016-07-13
1
-1
/
+1
*
Made the expansion order of hierarchy deterministic
Marcus Comstedt
2016-05-22
1
-3
/
+3
*
Added "yosys -D" feature
Clifford Wolf
2016-04-21
3
-8
/
+8
*
Cleanup abstract modules at end of "hierarchy -top"
Clifford Wolf
2016-03-21
1
-2
/
+0
*
Added "submod -copy"
Clifford Wolf
2016-01-08
1
-13
/
+28
*
Added "singleton" pass
Clifford Wolf
2015-11-07
2
-0
/
+102
*
Import more std:: stuff into Yosys namespace
Clifford Wolf
2015-10-25
1
-5
/
+5
*
Spell check (by Larry Doolittle)
Clifford Wolf
2015-08-14
1
-1
/
+1
*
Keep modules with $assume (like $assert)
Clifford Wolf
2015-07-25
1
-1
/
+1
*
Fixed trailing whitespaces
Clifford Wolf
2015-07-02
2
-5
/
+5
*
Added "dffinit", Support for initialized Xilinx DFF
Clifford Wolf
2015-04-04
1
-2
/
+2
*
documentation improvements
Clifford Wolf
2015-03-29
1
-1
/
+1
*
Added hierarchy -auto-top
Clifford Wolf
2015-03-18
1
-1
/
+33
*
Fixed bug in "hierarchy" for parametric designs
Clifford Wolf
2015-03-04
1
-20
/
+19
*
Cosmetic fixes in "hierarchy" for blackbox modules
Clifford Wolf
2015-02-15
1
-2
/
+4
*
Fixed pattern matching in "hierarchy -generate"
Clifford Wolf
2015-01-04
1
-2
/
+2
*
Added Yosys::{dict,nodict,vector} container types
Clifford Wolf
2014-12-26
1
-2
/
+2
*
Fixed off-by-one bug in "hierarchy -check" for positional module args
Clifford Wolf
2014-12-24
1
-2
/
+2
*
Checking existence of ports in "hierarchy -check"
Clifford Wolf
2014-12-19
1
-0
/
+13
*
Fixed bug in "hierarchy -top" with array of instances
Clifford Wolf
2014-11-27
1
-3
/
+10
*
Added log_warning() API
Clifford Wolf
2014-11-09
1
-2
/
+2
*
Various win32 / vs build fixes
Clifford Wolf
2014-10-17
1
-2
/
+2
*
Header changes so it will compile on VS
William Speirs
2014-10-17
1
-1
/
+5
*
Do not the 'z' modifier in format string (another win32 fix)
Clifford Wolf
2014-10-11
1
-1
/
+1
*
Moved patmatch() to yosys.cc
Clifford Wolf
2014-10-10
1
-1
/
+0
*
Replaced fnmatch() with patmatch()
Clifford Wolf
2014-10-10
1
-5
/
+4
*
set "keep" on modules with $assert cells in "hierarchy"
Clifford Wolf
2014-09-30
1
-0
/
+30
*
namespace Yosys
Clifford Wolf
2014-09-27
2
-11
/
+17
*
Corrected spelling mistakes found by lintian
Ruben Undheim
2014-09-06
1
-4
/
+4
*
Added module->ports
Clifford Wolf
2014-08-14
2
-4
/
+5
*
More bugfixes related to new RTLIL::IdString
Clifford Wolf
2014-08-02
1
-1
/
+1
*
More cleanups related to RTLIL::IdString usage
Clifford Wolf
2014-08-02
2
-20
/
+20
*
Renamed port access function on RTLIL::Cell, added param access functions
Clifford Wolf
2014-07-31
1
-1
/
+1
*
Added module->design and cell->module, wire->module pointers
Clifford Wolf
2014-07-31
2
-2
/
+2
*
Allow "hierarchy -generate" for $__ cells
Clifford Wolf
2014-07-29
1
-1
/
+3
*
Using log_assert() instead of assert()
Clifford Wolf
2014-07-28
2
-3
/
+3
*
Refactoring: Renamed RTLIL::Design::modules to modules_
Clifford Wolf
2014-07-27
2
-36
/
+36
*
Refactoring: Renamed RTLIL::Module::cells to cells_
Clifford Wolf
2014-07-27
2
-8
/
+8
*
Refactoring: Renamed RTLIL::Module::wires to wires_
Clifford Wolf
2014-07-27
2
-5
/
+5
*
Changed a lot of code to the new RTLIL::Wire constructors
Clifford Wolf
2014-07-26
2
-21
/
+23
*
Manual fixes for new cell connections API
Clifford Wolf
2014-07-26
2
-5
/
+5
*
Changed users of cell->connections_ to the new API (sed command)
Clifford Wolf
2014-07-26
2
-11
/
+11
*
Renamed RTLIL::{Module,Cell}::connections to connections_
Clifford Wolf
2014-07-26
2
-11
/
+11
*
Added copy-constructor-like module->addCell(name, other) method
Clifford Wolf
2014-07-26
1
-4
/
+1
*
Use only module->addCell() and module->remove() to create and delete cells
Clifford Wolf
2014-07-25
1
-8
/
+6
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