iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Small bugfix in uniquify pass	Claire Xenia Wolf	2022-12-21	1	-0/+1
*	Support importing verilog configurations using Verific	Miodrag Milanovic	2022-11-25	1	-1/+1
*	Makes sure to set initial_top when change, fixes #3462	Miodrag Milanovic	2022-08-26	1	-0/+1
*	Fitting help messages to 80 character width	KrystalDelusion	2022-08-24	1	-2/+2
*	Add the $anyinit cell and the formalff pass	Jannis Harder	2022-08-16	1	-0/+1
*	add hierarchy -smtcheck	Jacob Lifshay	2022-06-22	1	-7/+16
*	Reorder steps in -auto-top to fix synth command, fixes #3261	Miodrag Milanovic	2022-04-05	1	-13/+13
*	verilog: use derived module info to elaborate cell connections	Zachary Snow	2021-10-25	1	-0/+4
*	Split out logic for reprocessing an AstModule	Rupert Swarbrick	2021-10-25	1	-1/+1
*	Use new read_id_num helper function elsewhere in hierarchy.cc	Rupert Swarbrick	2021-07-20	1	-5/+6
*	Extract connection checking logic from expand_module in hierarchy.cc	Rupert Swarbrick	2021-07-20	1	-23/+64
*	Extract missing module support in hierarchy.cc to a helper function	Rupert Swarbrick	2021-07-14	1	-44/+68
*	Move interface expansion in hierarchy.cc into a helper class	Rupert Swarbrick	2021-06-16	1	-100/+189
*	Fixing old e-mail addresses and deadnames	Claire Xenia Wolf	2021-06-08	3	-3/+3
*	Sign extend port connections where necessary	Zachary Snow	2020-12-18	1	-2/+6
*	Validate parameters only when they are used	Miodrag Milanovic	2020-09-25	1	-5/+7
*	Replace "ILANG" with "RTLIL" everywhere.	whitequark	2020-08-26	1	-1/+1
*	Use C++11 final/override keywords.	whitequark	2020-06-18	3	-6/+6
*	Merge pull request #2089 from rswarbrick/modports	clairexen	2020-06-08	1	-13/+6
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\| *	Simplify a modport check in hierarchy.cc	Rupert Swarbrick	2020-05-26	1	-13/+6
* \|	Fix small typos in documentation for hierarchy command	Rupert Swarbrick	2020-05-28	1	-2/+2
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*	hierarchy: Convert positional parameters to named.	Marcelina Kościelnicka	2020-04-21	1	-3/+27
*	Use more descriptive variable name.	Alberto Gonzalez	2020-04-06	1	-2/+2
*	Clean up `passes/hierarchy/submod.cc`.	Alberto Gonzalez	2020-04-05	1	-25/+20
*	kernel: big fat patch to use more ID::, otherwise ID()	Eddie Hung	2020-04-02	3	-31/+31
*	kernel: use more ID::*	Eddie Hung	2020-04-02	2	-21/+21
*	Fix double deletion in `passes/hierarchy/hierarchy.cc`.	Alberto Gonzalez	2020-03-30	1	-1/+0
*	Clean up pseudo-private member usage in `passes/hierarchy/hierarchy.cc`.	Alberto Gonzalez	2020-03-19	1	-68/+63
*	Merge pull request #1519 from YosysHQ/eddie/submod_po	Claire Wolf	2020-03-03	1	-37/+99
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\| *	Use pool instead of std::set for determinism	Eddie Hung	2019-12-02	1	-1/+1
\| *	Move \init signal for non-port signals as long as internally driven	Eddie Hung	2019-11-28	1	-1/+1
\| *	Fix multiple driver issue	Eddie Hung	2019-11-27	1	-2/+7
\| *	Do not replace constants with same wire	Eddie Hung	2019-11-27	1	-7/+3
\| *	Cleanup	Eddie Hung	2019-11-27	1	-5/+3
\| *	Check for nullptr	Eddie Hung	2019-11-27	1	-1/+1
\| *	Stray log_dump	Eddie Hung	2019-11-27	1	-1/+0
\| *	Revert "submod to bitty rather bussy, for bussy wires used as input and output"	Eddie Hung	2019-11-27	1	-40/+71
\| *	Promote output wires in sigmap so that can be detected	Eddie Hung	2019-11-26	1	-8/+4
\| *	Fix submod -hidden	Eddie Hung	2019-11-26	1	-5/+6
\| *	Add -hidden option to submod	Eddie Hung	2019-11-26	1	-11/+25
\| *	Update docs with bullet points	Eddie Hung	2019-11-26	1	-10/+9
\| *	Move \init from source wire to submod if output port	Eddie Hung	2019-11-25	1	-0/+7
\| *	submod to bitty rather bussy, for bussy wires used as input and output	Eddie Hung	2019-11-22	1	-48/+39
\| *	Constant driven signals are also an input to submodules	Eddie Hung	2019-11-22	1	-2/+10
\| *	Oops	Eddie Hung	2019-11-22	1	-1/+0
\| *	sigmap(wire) should inherit port_output status of POs	Eddie Hung	2019-11-22	1	-1/+19
* \|	sv: Improve handling of wildcard port connections	David Shah	2020-02-02	1	-3/+3
* \|	hierarchy: Correct handling of wildcard port connections with default values	David Shah	2020-02-02	1	-7/+14
* \|	hierarchy: Resolve SV wildcard port connections	David Shah	2020-02-02	1	-3/+62
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*	Adopt @cliffordwolf's suggestion	Eddie Hung	2019-09-03	1	-10/+3