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author | Clifford Wolf <clifford@clifford.at> | 2014-10-17 14:01:47 +0200 |
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committer | Clifford Wolf <clifford@clifford.at> | 2014-10-17 14:01:47 +0200 |
commit | 468ae923748a01b2763bafa3cf5fba883fe06479 (patch) | |
tree | f80cf488e9a2f07592c2444b853d0c53edce7a20 /passes/hierarchy | |
parent | 973d37673377c3ddba8020e718e4cd6174379175 (diff) | |
download | yosys-468ae923748a01b2763bafa3cf5fba883fe06479.tar.gz yosys-468ae923748a01b2763bafa3cf5fba883fe06479.tar.bz2 yosys-468ae923748a01b2763bafa3cf5fba883fe06479.zip |
Various win32 / vs build fixes
Diffstat (limited to 'passes/hierarchy')
-rw-r--r-- | passes/hierarchy/hierarchy.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc index 2a7e96346..0ea26eb9e 100644 --- a/passes/hierarchy/hierarchy.cc +++ b/passes/hierarchy/hierarchy.cc @@ -174,7 +174,7 @@ bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_check for (auto &dir : libdirs) { filename = dir + "/" + RTLIL::unescape_id(cell->type) + ".v"; - if (access(filename.c_str(), F_OK) == 0) { + if (check_file_exists(filename)) { std::vector<std::string> args; args.push_back(filename); Frontend::frontend_call(design, NULL, filename, "verilog"); @@ -182,7 +182,7 @@ bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_check } filename = dir + "/" + RTLIL::unescape_id(cell->type) + ".il"; - if (access(filename.c_str(), F_OK) == 0) { + if (check_file_exists(filename)) { std::vector<std::string> args; args.push_back(filename); Frontend::frontend_call(design, NULL, filename, "ilang"); |