aboutsummaryrefslogtreecommitdiffstats
path: root/passes/hierarchy
diff options
context:
space:
mode:
authorClifford Wolf <clifford@clifford.at>2014-07-26 00:38:44 +0200
committerClifford Wolf <clifford@clifford.at>2014-07-26 00:38:44 +0200
commit4755e14e7b9ba57ea21bec4c0d0b3ac6080307e4 (patch)
treee77060cca5dcdb2bff334096fe55981208a57ab2 /passes/hierarchy
parent2bec47a4045d23d46e7d300cbf80b2dce1a549a9 (diff)
downloadyosys-4755e14e7b9ba57ea21bec4c0d0b3ac6080307e4.tar.gz
yosys-4755e14e7b9ba57ea21bec4c0d0b3ac6080307e4.tar.bz2
yosys-4755e14e7b9ba57ea21bec4c0d0b3ac6080307e4.zip
Added copy-constructor-like module->addCell(name, other) method
Diffstat (limited to 'passes/hierarchy')
-rw-r--r--passes/hierarchy/submod.cc5
1 files changed, 1 insertions, 4 deletions
diff --git a/passes/hierarchy/submod.cc b/passes/hierarchy/submod.cc
index 204f899a0..be580ca04 100644
--- a/passes/hierarchy/submod.cc
+++ b/passes/hierarchy/submod.cc
@@ -162,10 +162,7 @@ struct SubmodWorker
}
for (RTLIL::Cell *cell : submod.cells) {
- RTLIL::Cell *new_cell = new_mod->addCell(cell->name, cell->type);
- new_cell->connections = cell->connections;
- new_cell->parameters = cell->parameters;
- new_cell->attributes = cell->attributes;
+ RTLIL::Cell *new_cell = new_mod->addCell(cell->name, cell);
for (auto &conn : new_cell->connections)
for (auto &bit : conn.second)
if (bit.wire != NULL) {