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| author | Clifford Wolf <clifford@clifford.at> | 2014-07-26 15:57:57 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-07-26 15:58:23 +0200 |
| commit | f8fdc47d3361c1a3445a9357ca26cfe75907d6b0 (patch) | |
| tree | e4b1c2f97db2c317f8b986635141dfd7bb8e78d8 /passes/hierarchy | |
| parent | b7dda723022ad00c6c0089be888eab319953faa8 (diff) | |
| download | yosys-f8fdc47d3361c1a3445a9357ca26cfe75907d6b0.tar.gz yosys-f8fdc47d3361c1a3445a9357ca26cfe75907d6b0.tar.bz2 yosys-f8fdc47d3361c1a3445a9357ca26cfe75907d6b0.zip | |
Manual fixes for new cell connections API
Diffstat (limited to 'passes/hierarchy')
| -rw-r--r-- | passes/hierarchy/hierarchy.cc | 4 | ||||
| -rw-r--r-- | passes/hierarchy/submod.cc | 6 |
2 files changed, 5 insertions, 5 deletions
diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc index 5937373fa..76b667b86 100644 --- a/passes/hierarchy/hierarchy.cc +++ b/passes/hierarchy/hierarchy.cc @@ -219,7 +219,7 @@ static bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool fla RTLIL::Module *mod = design->modules[cell->type]; - for (auto &conn : cell->connections()) { + for (auto &conn : cell->connections_) { int conn_size = conn.second.size(); std::string portname = conn.first; if (portname.substr(0, 1) == "$") { @@ -519,7 +519,7 @@ struct HierarchyPass : public Pass { new_connections[pos_map.at(key)] = conn.second; } else new_connections[conn.first] = conn.second; - cell->connections() = new_connections; + cell->connections_ = new_connections; } } diff --git a/passes/hierarchy/submod.cc b/passes/hierarchy/submod.cc index d72ebb127..ef4a9f16d 100644 --- a/passes/hierarchy/submod.cc +++ b/passes/hierarchy/submod.cc @@ -65,7 +65,7 @@ struct SubmodWorker flag_found_something = true; } - void flag_signal(RTLIL::SigSpec &sig, bool create, bool set_int_driven, bool set_int_used, bool set_ext_driven, bool set_ext_used) + void flag_signal(const RTLIL::SigSpec &sig, bool create, bool set_int_driven, bool set_int_used, bool set_ext_driven, bool set_ext_used) { for (auto &c : sig.chunks()) if (c.wire != NULL) @@ -163,7 +163,7 @@ struct SubmodWorker for (RTLIL::Cell *cell : submod.cells) { RTLIL::Cell *new_cell = new_mod->addCell(cell->name, cell); - for (auto &conn : new_cell->connections()) + for (auto &conn : new_cell->connections_) for (auto &bit : conn.second) if (bit.wire != NULL) { assert(wire_flags.count(bit.wire) > 0); @@ -180,7 +180,7 @@ struct SubmodWorker RTLIL::Wire *old_wire = it.first; RTLIL::Wire *new_wire = it.second.new_wire; if (new_wire->port_id > 0) - new_cell->connections()[new_wire->name] = RTLIL::SigSpec(old_wire); + new_cell->set(new_wire->name, RTLIL::SigSpec(old_wire)); } } |