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* Add "hierarchy -chparam" support for non-verific top modulesClifford Wolf2019-05-031-12/+35
* log_warning_noprefix -> log_warning as per reviewEddie Hung2019-05-031-1/+1
* WIP -chparam support for hierarchy when verificEddie Hung2019-05-031-7/+24
* Add "whitebox" attribute, add "read_verilog -wb"Clifford Wolf2019-04-182-6/+6
* Add "hdlname" attributeClifford Wolf2019-03-261-0/+2
* Only run derive on blackbox modules when ports have dynamic sizeClifford Wolf2019-03-021-1/+1
* Minor changes ontop of 71bcc4c: Remove hierarchy warning that is redundant to...Clifford Wolf2019-02-241-5/+1
* Address requested changes - don't require non-$ name.Jim Lawson2019-02-221-7/+7
* Fix normal (non-array) hierarchy -auto-top.Jim Lawson2019-02-191-9/+9
* Define basic_cell_type() function and use it to derive the cell type for arra...Jim Lawson2019-02-151-10/+40
* Fix typographical and grammatical errors and inconsistencies.whitequark2019-01-021-1/+1
* Refactor code to avoid code duplication + added commentsRuben Undheim2018-10-201-2/+5
* Support for SystemVerilog interfaces as a port in the top level module + test...Ruben Undheim2018-10-201-5/+36
* Documentation improvements etc.Ruben Undheim2018-10-131-27/+38
* Support for 'modports' for System Verilog interfacesRuben Undheim2018-10-121-1/+13
* Synthesis support for SystemVerilog interfacesRuben Undheim2018-10-121-7/+165
* Consistent use of 'override' for virtual methods in derived classes.Henner Zeller2018-07-203-6/+6
* Add automatic verific import in hierarchy commandClifford Wolf2018-06-201-1/+19
* Bugfix in handling of array instances with empty portsClifford Wolf2018-05-311-1/+1
* Add "hierarchy -simcheck"Clifford Wolf2018-05-121-7/+23
* Chenged "extensions_map" to "extensions_list" in hierarchy.ccClifford Wolf2018-03-271-2/+2
* passes/hierarchy: Reduce code duplication in expand_moduleSergi Granell2018-03-271-15/+13
* Add .sv support to "hierarchy -libdir"Clifford Wolf2018-03-261-0/+6
* Bugfix in hierarchy blackbox module port width handlingClifford Wolf2018-01-071-1/+2
* Bugfix in hierarchy handling of blackbox module portsClifford Wolf2018-01-051-5/+4
* Temporarily derive blackbox modules in hierarchy to evaluate port widthsClifford Wolf2018-01-041-1/+14
* Rename "singleton" pass to "uniquify"Clifford Wolf2017-08-202-20/+21
* Add error for cell output ports that are connected to constantsClifford Wolf2017-07-221-20/+21
* Fix handling of empty cell port assignments (i.e. ignore them)Clifford Wolf2017-07-211-0/+3
* Add $live and $fair cell types, add support for s_eventually keywordClifford Wolf2017-02-251-1/+1
* Do not fix port widths on any blackbox instancesClifford Wolf2017-02-131-1/+1
* Do not eagerly fix port widths on parameterized cellsClifford Wolf2017-02-121-0/+3
* Add $cover cell type and SVA cover() supportClifford Wolf2017-02-041-1/+1
* passes/hierarchy: delete some dead codeAustin Seipp2017-01-151-4/+0
* Added cell port resizing to hierarchy passClifford Wolf2017-01-011-0/+56
* Added support for hierarchical defparamsClifford Wolf2016-11-151-1/+1
* Minor bugfix in submodClifford Wolf2016-11-091-0/+1
* Bugfix in "hierarchy -check"Clifford Wolf2016-11-021-1/+1
* Added avail params to ilang format, check module params in 'hierarchy -check'Clifford Wolf2016-10-221-0/+4
* Removed $predict againClifford Wolf2016-08-281-1/+1
* Fixed use-after-free dict<> usage pattern in hierarchy.ccClifford Wolf2016-08-161-1/+3
* After reading the SV spec, using non-standard predict() instead of expect()Clifford Wolf2016-07-211-1/+1
* Added basic support for $expect cellsClifford Wolf2016-07-131-1/+1
* Made the expansion order of hierarchy deterministicMarcus Comstedt2016-05-221-3/+3
* Added "yosys -D" featureClifford Wolf2016-04-213-8/+8
* Cleanup abstract modules at end of "hierarchy -top"Clifford Wolf2016-03-211-2/+0
* Added "submod -copy"Clifford Wolf2016-01-081-13/+28
* Added "singleton" passClifford Wolf2015-11-072-0/+102
* Import more std:: stuff into Yosys namespaceClifford Wolf2015-10-251-5/+5
* Spell check (by Larry Doolittle)Clifford Wolf2015-08-141-1/+1