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| author | Clifford Wolf <clifford@clifford.at> | 2017-02-25 10:36:39 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2017-02-25 10:36:39 +0100 |
| commit | 5f1d0b1024981b6ede2988bf8c5812b37c87d0e9 (patch) | |
| tree | 75e48829241c9c65b5c9c7a34cc21048285ea48b /passes/hierarchy | |
| parent | 7af9727f78263d2fc41178396791f51a680acdfa (diff) | |
| download | yosys-5f1d0b1024981b6ede2988bf8c5812b37c87d0e9.tar.gz yosys-5f1d0b1024981b6ede2988bf8c5812b37c87d0e9.tar.bz2 yosys-5f1d0b1024981b6ede2988bf8c5812b37c87d0e9.zip | |
Add $live and $fair cell types, add support for s_eventually keyword
Diffstat (limited to 'passes/hierarchy')
| -rw-r--r-- | passes/hierarchy/hierarchy.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc index 3534cbcdb..d71e9c574 100644 --- a/passes/hierarchy/hierarchy.cc +++ b/passes/hierarchy/hierarchy.cc @@ -313,7 +313,7 @@ bool set_keep_assert(std::map<RTLIL::Module*, bool> &cache, RTLIL::Module *mod) if (cache.count(mod) == 0) for (auto c : mod->cells()) { RTLIL::Module *m = mod->design->module(c->type); - if ((m != nullptr && set_keep_assert(cache, m)) || c->type.in("$assert", "$assume", "$cover")) + if ((m != nullptr && set_keep_assert(cache, m)) || c->type.in("$assert", "$assume", "$live", "$fair", "$cover")) return cache[mod] = true; } return cache[mod]; |