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| author | Austin Seipp <aseipp@pobox.com> | 2017-01-15 16:39:12 -0600 |
|---|---|---|
| committer | Austin Seipp <aseipp@pobox.com> | 2017-01-15 16:39:12 -0600 |
| commit | 6781543244105c880eb847dc59d1d801b10bdc4f (patch) | |
| tree | 86b063be369a00b7f76cf1f2529bcf33495b51a4 /passes/hierarchy | |
| parent | 78f65f89ffc1d5c5237009c19e84e625ce3085aa (diff) | |
| download | yosys-6781543244105c880eb847dc59d1d801b10bdc4f.tar.gz yosys-6781543244105c880eb847dc59d1d801b10bdc4f.tar.bz2 yosys-6781543244105c880eb847dc59d1d801b10bdc4f.zip | |
passes/hierarchy: delete some dead code
Signed-off-by: Austin Seipp <aseipp@pobox.com>
Diffstat (limited to 'passes/hierarchy')
| -rw-r--r-- | passes/hierarchy/hierarchy.cc | 4 |
1 files changed, 0 insertions, 4 deletions
diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc index 337af7fd7..f1c4a1d3b 100644 --- a/passes/hierarchy/hierarchy.cc +++ b/passes/hierarchy/hierarchy.cc @@ -175,16 +175,12 @@ bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_check { filename = dir + "/" + RTLIL::unescape_id(cell->type) + ".v"; if (check_file_exists(filename)) { - std::vector<std::string> args; - args.push_back(filename); Frontend::frontend_call(design, NULL, filename, "verilog"); goto loaded_module; } filename = dir + "/" + RTLIL::unescape_id(cell->type) + ".il"; if (check_file_exists(filename)) { - std::vector<std::string> args; - args.push_back(filename); Frontend::frontend_call(design, NULL, filename, "ilang"); goto loaded_module; } |