diff options
| author | Clifford Wolf <clifford@clifford.at> | 2018-03-26 21:19:00 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2018-03-26 21:19:00 +0200 |
| commit | 491c352da7b656aa3979754e0a03182dfaabdd13 (patch) | |
| tree | 1fa9e9c6149e7f001fe8b4cd130deba4267e055c /passes/hierarchy | |
| parent | 315d5e32bfb63a2b4be2dc5e729125c420b164a4 (diff) | |
| download | yosys-491c352da7b656aa3979754e0a03182dfaabdd13.tar.gz yosys-491c352da7b656aa3979754e0a03182dfaabdd13.tar.bz2 yosys-491c352da7b656aa3979754e0a03182dfaabdd13.zip | |
Add .sv support to "hierarchy -libdir"
Diffstat (limited to 'passes/hierarchy')
| -rw-r--r-- | passes/hierarchy/hierarchy.cc | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc index 898763c64..71b0cf622 100644 --- a/passes/hierarchy/hierarchy.cc +++ b/passes/hierarchy/hierarchy.cc @@ -179,6 +179,12 @@ bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_check goto loaded_module; } + filename = dir + "/" + RTLIL::unescape_id(cell->type) + ".sv"; + if (check_file_exists(filename)) { + Frontend::frontend_call(design, NULL, filename, "verilog -sv"); + goto loaded_module; + } + filename = dir + "/" + RTLIL::unescape_id(cell->type) + ".il"; if (check_file_exists(filename)) { Frontend::frontend_call(design, NULL, filename, "ilang"); |