diff options
| author | Zachary Snow <zach@zachjs.com> | 2021-10-19 18:46:26 -0600 |
|---|---|---|
| committer | Zachary Snow <zachary.j.snow@gmail.com> | 2021-10-25 18:25:50 -0700 |
| commit | e833c6a418103feb30f0cc3e5c482da00ee9f820 (patch) | |
| tree | ef7d028ed17200f04558f3d2426f3db7ef6134cd /passes/hierarchy | |
| parent | bd16d01c0eed5c96a241e6ee9e56b8f7890319a1 (diff) | |
| download | yosys-e833c6a418103feb30f0cc3e5c482da00ee9f820.tar.gz yosys-e833c6a418103feb30f0cc3e5c482da00ee9f820.tar.bz2 yosys-e833c6a418103feb30f0cc3e5c482da00ee9f820.zip | |
verilog: use derived module info to elaborate cell connections
- Attempt to lookup a derived module if it potentially contains a port
connection with elaboration ambiguities
- Mark the cell if module has not yet been derived
- This can be extended to implement automatic hierarchical port
connections in a future change
Diffstat (limited to 'passes/hierarchy')
| -rw-r--r-- | passes/hierarchy/hierarchy.cc | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc index 1e69ab903..440881f19 100644 --- a/passes/hierarchy/hierarchy.cc +++ b/passes/hierarchy/hierarchy.cc @@ -558,6 +558,10 @@ bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_check return did_something; } + // Now that modules have been derived, we may want to reprocess this + // module given the additional available context. + if (module->reprocess_if_necessary(design)) + return true; for (auto &it : array_cells) { |