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| author | Eddie Hung <eddie@fpgeh.com> | 2019-11-22 17:23:51 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-11-22 17:23:51 -0800 |
| commit | 8119383f8198d621e88b54fdd615e352ecc576bb (patch) | |
| tree | 336896c02d9bbe075e7172ce2f5a35a42205f553 /passes/hierarchy | |
| parent | 4fdcf8f7d73d0e577815ab50a3e0255f4bfd2154 (diff) | |
| download | yosys-8119383f8198d621e88b54fdd615e352ecc576bb.tar.gz yosys-8119383f8198d621e88b54fdd615e352ecc576bb.tar.bz2 yosys-8119383f8198d621e88b54fdd615e352ecc576bb.zip | |
Constant driven signals are also an input to submodules
Diffstat (limited to 'passes/hierarchy')
| -rw-r--r-- | passes/hierarchy/submod.cc | 12 |
1 files changed, 10 insertions, 2 deletions
diff --git a/passes/hierarchy/submod.cc b/passes/hierarchy/submod.cc index 707bc26b3..a1fac9b79 100644 --- a/passes/hierarchy/submod.cc +++ b/passes/hierarchy/submod.cc @@ -33,7 +33,7 @@ struct SubmodWorker CellTypes ct; RTLIL::Design *design; RTLIL::Module *module; - pool<Wire*> outputs; + pool<Wire*> constants, outputs; bool copy_mode; std::string opt_name; @@ -125,7 +125,7 @@ struct SubmodWorker RTLIL::Wire *wire = it.first; wire_flags_t &flags = it.second; - if (wire->port_input) + if (wire->port_input || constants.count(wire)) flags.is_ext_driven = true; if (wire->port_output || outputs.count(wire)) flags.is_ext_used = true; @@ -235,6 +235,14 @@ struct SubmodWorker outputs.insert(c.wire); } } + for (auto wire : module->wires()) { + auto sig = sigmap(wire); + for (auto c : sig.chunks()) { + if (c.wire) + continue; + constants.insert(wire); + } + } if (opt_name.empty()) { |