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| author | whitequark <whitequark@whitequark.org> | 2020-08-26 17:29:32 +0000 |
|---|---|---|
| committer | whitequark <whitequark@whitequark.org> | 2020-08-26 17:29:32 +0000 |
| commit | 00e7dec7f54eb2e4f18112e5c0007a55287fdf8e (patch) | |
| tree | e0db11dfa158264e270f30e2b677e319f09b6047 /passes/hierarchy | |
| parent | 4f2b78e19af3a2d342efe9780e220282b7a3a046 (diff) | |
| download | yosys-00e7dec7f54eb2e4f18112e5c0007a55287fdf8e.tar.gz yosys-00e7dec7f54eb2e4f18112e5c0007a55287fdf8e.tar.bz2 yosys-00e7dec7f54eb2e4f18112e5c0007a55287fdf8e.zip | |
Replace "ILANG" with "RTLIL" everywhere.
The only difference between "RTLIL" and "ILANG" is that the latter is
the text representation of the former, as opposed to the in-memory
graph representation. This distinction serves no purpose but confuses
people: it is not obvious that the ILANG backend writes RTLIL graphs.
Passes `write_ilang` and `read_ilang` are provided as aliases to
`write_rtlil` and `read_rtlil` for compatibility.
Diffstat (limited to 'passes/hierarchy')
| -rw-r--r-- | passes/hierarchy/hierarchy.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc index a2a428d15..90b25949d 100644 --- a/passes/hierarchy/hierarchy.cc +++ b/passes/hierarchy/hierarchy.cc @@ -224,7 +224,7 @@ bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_check { {".v", "verilog"}, {".sv", "verilog -sv"}, - {".il", "ilang"} + {".il", "rtlil"} }; for (auto &ext : extensions_list) |