iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
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*	Fixed fsm_extract for wreduced muxes	Clifford Wolf	2014-08-08	1	-8/+25
*	No implicit conversion from IdString to anything else	Clifford Wolf	2014-08-02	1	-1/+1
*	More cleanups related to RTLIL::IdString usage	Clifford Wolf	2014-08-02	3	-4/+4
*	Renamed port access function on RTLIL::Cell, added param access functions	Clifford Wolf	2014-07-31	6	-84/+84
*	Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace	Clifford Wolf	2014-07-31	1	-2/+2
*	Using log_assert() instead of assert()	Clifford Wolf	2014-07-28	2	-4/+4
*	Added log_cmd_error_expection	Clifford Wolf	2014-07-27	1	-4/+1
*	Refactoring: Renamed RTLIL::Design::modules to modules_	Clifford Wolf	2014-07-27	8	-8/+8
*	Refactoring: Renamed RTLIL::Module::cells to cells_	Clifford Wolf	2014-07-27	8	-13/+13
*	Refactoring: Renamed RTLIL::Module::wires to wires_	Clifford Wolf	2014-07-27	2	-5/+5
*	Changed a lot of code to the new RTLIL::Wire constructors	Clifford Wolf	2014-07-26	2	-19/+6
*	Added RTLIL::Cell::has(portname)	Clifford Wolf	2014-07-26	3	-10/+10
*	Manual fixes for new cell connections API	Clifford Wolf	2014-07-26	3	-9/+17
*	Changed users of cell->connections_ to the new API (sed command)	Clifford Wolf	2014-07-26	6	-94/+94
*	Renamed RTLIL::{Module,Cell}::connections to connections_	Clifford Wolf	2014-07-26	6	-94/+94
*	Use only module->addCell() and module->remove() to create and delete cells	Clifford Wolf	2014-07-25	3	-60/+19
*	Various small fixes (from gcc compiler warnings)	Clifford Wolf	2014-07-23	1	-4/+4
*	Removed RTLIL::SigSpec::optimize()	Clifford Wolf	2014-07-23	1	-5/+0
*	Refactoring {SigSpec\|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3	Clifford Wolf	2014-07-23	1	-8/+8
*	Refactoring {SigSpec\|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 2/3	Clifford Wolf	2014-07-23	1	-8/+8
*	SigSpec refactoring: cleanup of old SigSpec usage in fsm_* commands	Clifford Wolf	2014-07-22	3	-38/+19
*	fixed memory leak in fsm_opt	Clifford Wolf	2014-07-22	1	-1/+3
*	SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created...	Clifford Wolf	2014-07-22	1	-2/+2
*	SigSpec refactoring: using the accessor functions everywhere	Clifford Wolf	2014-07-22	6	-58/+58
*	SigSpec refactoring: renamed chunks and width to __chunks and __width	Clifford Wolf	2014-07-22	6	-58/+58
*	Merged a few fixes for non-posix systems from github.com/Siesh1oo/yosys	Clifford Wolf	2014-03-11	1	-1/+2
*	Fixes in fsm detect/extract for better detection of non-fsm circuits	Clifford Wolf	2013-12-06	2	-4/+4
*	Replaced RTLIL::Const::str with generic decoder method	Clifford Wolf	2013-12-04	6	-12/+12
*	Added detection for endless recursion in fsm_detect pass	Clifford Wolf	2013-10-30	1	-4/+15
*	Some fixes to improve determinism	Clifford Wolf	2013-08-09	2	-28/+31
*	Sort ctrl signals in fsm_extract	Clifford Wolf	2013-08-08	1	-0/+3
*	Renamed opt_rmunused to opt_clean	Clifford Wolf	2013-06-05	3	-7/+7
*	Added -nodetect option to fsm pass	Clifford Wolf	2013-05-24	1	-2/+8
*	Improved FSM one-hot encoding, added binary encoding	Clifford Wolf	2013-05-24	3	-44/+85
*	fsm_export: optionally use binary state encoding as state names instead of	Johann Glaser	2013-04-05	1	-6/+23
*	fsm_export: specify KISS filename on command line	Johann Glaser	2013-04-05	1	-5/+20
*	Improved method for finding fsm_expand candidates	Clifford Wolf	2013-03-25	1	-5/+7
*	Changed fsm_expand to merge multiplexers more aggressively	Clifford Wolf	2013-03-24	1	-1/+4
*	fixed typos	Johann Glaser	2013-03-18	2	-4/+4
*	Added [[CITE]] tags to abc and fsm_extract passes	Clifford Wolf	2013-03-15	1	-1/+6
*	Added help messages for fsm_* passes	Clifford Wolf	2013-03-01	9	-41/+193
*	"fsm_export" pass: fix KISS file generation.	Martin Schmölzer	2013-02-23	1	-4/+4
*	Add support for "fsm_export" synthesis attributes to fsm_export pass.	Martin Schmölzer	2013-01-08	1	-46/+86
*	Copy attributes from state signal to fsm cell	Clifford Wolf	2013-01-05	1	-0/+1
*	initial import	Clifford Wolf	2013-01-05	11	-0/+1957