| Commit message (Collapse) | Author | Age | Files | Lines | ||
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| | * | | | Move ConstEvalAig to aigerparse.cc | Eddie Hung | 2019-06-13 | 1 | -157/+0 | |
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| | * | | | More slimming | Eddie Hung | 2019-06-13 | 1 | -35/+35 | |
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| | * | | | Add ConstEvalAig specialised for AIGs | Eddie Hung | 2019-06-13 | 1 | -0/+157 | |
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| | * | | | Merge remote-tracking branch 'origin/master' into xaig | Eddie Hung | 2019-06-12 | 9 | -21/+187 | |
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| | * | | | | Remove kernel/cost.cc since master has refactored it | Eddie Hung | 2019-04-22 | 1 | -75/+0 | |
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| | * | | | | Merge remote-tracking branch 'origin/master' into xaig | Eddie Hung | 2019-04-22 | 9 | -5/+289 | |
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| | * \ \ \ \ | Merge remote-tracking branch 'origin/master' into xaig | Eddie Hung | 2019-04-20 | 2 | -3/+6 | |
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| | * | | | | | | Ignore 'whitebox' attr in flatten with "-wb" option | Eddie Hung | 2019-04-18 | 1 | -2/+2 | |
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| | * | | | | | | Merge remote-tracking branch 'origin/clifford/whitebox' into xaig | Eddie Hung | 2019-04-18 | 2 | -3/+7 | |
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| | * \ \ \ \ \ \ | Merge branch 'master' into xaig | Eddie Hung | 2019-04-08 | 7 | -27/+151 | |
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| | * \ \ \ \ \ \ \ | Merge remote-tracking branch 'origin/master' into xaig | Eddie Hung | 2019-02-26 | 1 | -2/+16 | |
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| | * | | | | | | | | | Add IdString::ends_with() | Eddie Hung | 2019-02-26 | 1 | -0/+6 | |
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| | * | | | | | | | | | Merge remote-tracking branch 'origin/master' into xaig | Eddie Hung | 2019-02-21 | 1 | -0/+3 | |
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| | * | | | | | | | | | | Refactor kernel/cost.h definition into cost.cc | Eddie Hung | 2019-02-08 | 2 | -49/+77 | |
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| * | | | | | | | | | | | Merge remote-tracking branch 'upstream/master' | Bogdan Vukobratovic | 2019-06-27 | 1 | -0/+1 | |
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| | * | | | | | | | | | | Add a few more filename rewrites | Ben Widawsky | 2019-06-20 | 1 | -0/+1 | |
| | | |_|_|_|_|_|_|_|/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This now allows a full pipeline to work, something such as: yosys -p "synth_ecp5 -json ~/work/fpga/prjtrellis/examples/ecp5_evn/blinky.v" Otherwise, you will get something along the lines of: ERROR: Can't open output file `~/work/fpga/prjtrellis/examples/ecp5_evn/blinky.v' for writing: No such file or directory Signed-off-by: Ben Widawsky <ben@bwidawsk.net> | |||||
| * | | | | | | | | | | Merge branch 'master' of https://github.com/bogdanvuk/yosys into ↵ | Clifford Wolf | 2019-06-20 | 1 | -5/+4 | |
| |\ \ \ \ \ \ \ \ \ \ | |/ / / / / / / / / |/| | | | | | | | | | | | | | | | | | | | clifford/ext1046 | |||||
| | * | | | | | | | | | Move netlist helper module to passes/opt for the time being | Bogdan Vukobratovic | 2019-06-14 | 1 | -317/+0 | |
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| | * | | | | | | | | | Merge remote-tracking branch 'upstream/master' | Bogdan Vukobratovic | 2019-06-14 | 3 | -1/+14 | |
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| | * | | | | | | | | | Prepare for situation when port of the signal cannot be found | Bogdan Vukobratovic | 2019-06-14 | 1 | -1/+7 | |
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| | * | | | | | | | | | Implement disconnection of constant register bits | Bogdan Vukobratovic | 2019-06-13 | 1 | -32/+85 | |
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| | * | | | | | | | | | Pass SigBit by value to Netlist algorithms | Bogdan Vukobratovic | 2019-06-13 | 1 | -65/+84 | |
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| | * | | | | | | | | | Rename satgen_algo.h -> algo.h, code cleanup and refactoring | Bogdan Vukobratovic | 2019-06-12 | 3 | -206/+243 | |
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| | * | | | | | | | | | Generate satgen instance instead of calling sat pass | Bogdan Vukobratovic | 2019-06-11 | 1 | -1/+44 | |
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| | * | | | | | | | | | Refactor driver map generation | Bogdan Vukobratovic | 2019-06-10 | 1 | -0/+158 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Implement iterators over the driver map that enumerate signals and cells within the cones of the signal | |||||
| * | | | | | | | | | | Merge pull request #1100 from bwidawsk/home | Clifford Wolf | 2019-06-19 | 1 | -0/+4 | |
| |\ \ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | Support ~ in filename parsing | |||||
| | * | | | | | | | | | | Support ~ for home directory | Ben Widawsky | 2019-06-18 | 1 | -0/+4 | |
| | | |/ / / / / / / / | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is tested on Linux only v2: Wrap functioanlity in ifndef _WIN32 (eddiehung) Find '~/' instead of '~' (cliffordwolf) Signed-off-by: Ben Widawsky <ben@bwidawsk.net> | |||||
| * / | | | | | | | | | In RTLIL::Module::check(), check process invariants. | whitequark | 2019-06-19 | 1 | -1/+28 | |
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| * | | | | | | | | | Fixes and cleanups in AST_TECALL handling | Clifford Wolf | 2019-06-07 | 1 | -4/+4 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | | | | | | | | Merge branch 'pr_elab_sys_tasks' of https://github.com/udif/yosys into ↵ | Clifford Wolf | 2019-06-07 | 2 | -0/+12 | |
| |\ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | clifford/pr983 | |||||
| | * | | | | | | | | | Initial implementation of elaboration system tasks | Udi Finkelstein | 2019-05-03 | 2 | -0/+12 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | (IEEE1800-2017 section 20.11) This PR allows us to use $info/$warning/$error/$fatal **at elaboration time** within a generate block. This is very useful to stop a synthesis of a parametrized block when an illegal combination of parameters is chosen. | |||||
| * | | | | | | | | | | Refactor hierarchy wand/wor handling | Clifford Wolf | 2019-05-28 | 1 | -0/+1 | |
| | |/ / / / / / / / |/| | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | | | | | | | | Fix handling of warning and error messages within log_make_debug-blocks | Clifford Wolf | 2019-05-22 | 1 | -0/+9 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | | | | | | | | Add rewrite_sigspecs2, Improve remove() wires | Clifford Wolf | 2019-05-15 | 2 | -7/+82 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | | | | | | | | Merge pull request #991 from kristofferkoch/gcc9-warnings | Clifford Wolf | 2019-05-08 | 1 | -0/+3 | |
| |\ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | Fix all warnings that occurred when compiling with gcc9 | |||||
| | * | | | | | | | | | Fix all warnings that occurred when compiling with gcc9 | Kristoffer Ellersgaard Koch | 2019-05-08 | 1 | -0/+3 | |
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| * | | | | | | | | | Merge pull request #998 from mdaiter/get_bool_attribute_opts | Clifford Wolf | 2019-05-08 | 1 | -4/+8 | |
| |\ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | Minor optimization to get_attribute_bool | |||||
| | * | | | | | | | | | Minor optimization to get_attribute_bool | Matthew Daiter | 2019-05-07 | 1 | -4/+8 | |
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| * | | | | | | | | | | Optimize ceil_log2 function | Matthew Daiter | 2019-05-07 | 2 | -3/+5 | |
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| * | | | | | | | | | Improve write_verilog specify support | Clifford Wolf | 2019-05-04 | 1 | -1/+1 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | | | | | | | | Merge remote-tracking branch 'origin/master' into clifford/specify | Eddie Hung | 2019-05-03 | 4 | -3/+18 | |
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| | * | | | | | | | | Fix performance bug in RTLIL::SigSpec::operator==(), fixes #970 | Clifford Wolf | 2019-04-30 | 1 | -1/+1 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | * | | | | | | | | fix codestyle formatting | Oleg Endo | 2019-04-29 | 3 | -14/+14 | |
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| | * | | | | | | | | escape spaces with backslash when writing dep file | Oleg Endo | 2019-04-29 | 3 | -2/+17 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | filenames are sparated by spaces in the dep file. if a filename in the dep file contains spaces they must be escaped, otherwise the tool that reads the dep file will see multiple wrong filenames. | |||||
| * | | | | | | | | | Improve $specrule interface | Clifford Wolf | 2019-04-23 | 1 | -2/+2 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | | | | | | | | Improve $specrule interface | Clifford Wolf | 2019-04-23 | 1 | -1/+2 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | | | | | | | | Add $specrule cells for $setup/$hold/$skew specify rules | Clifford Wolf | 2019-04-23 | 2 | -0/+17 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | | | | | | | | Rename T_{RISE,FALL}_AVG to T_{RISE,FALL}_TYP to better match verilog std ↵ | Clifford Wolf | 2019-04-23 | 1 | -2/+2 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | nomenclature Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | | | | | | | | Add CellTypes support for $specify2 and $specify3 | Clifford Wolf | 2019-04-23 | 1 | -0/+3 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | | | | | | | | Add InternalCellChecker support for $specify2 and $specify3 | Clifford Wolf | 2019-04-23 | 1 | -7/+21 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
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