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| author | Clifford Wolf <clifford@clifford.at> | 2019-05-28 16:43:25 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2019-05-28 16:43:25 +0200 |
| commit | ba2185ead89fdb6afeec6043ab18f2e045d80247 (patch) | |
| tree | 87a6d9493dfaa3a0e08d88cfb497d20283881d57 /kernel | |
| parent | e3ebac44df5bcbd976c7f88f2192d69a337ac3bf (diff) | |
| download | yosys-ba2185ead89fdb6afeec6043ab18f2e045d80247.tar.gz yosys-ba2185ead89fdb6afeec6043ab18f2e045d80247.tar.bz2 yosys-ba2185ead89fdb6afeec6043ab18f2e045d80247.zip | |
Refactor hierarchy wand/wor handling
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Diffstat (limited to 'kernel')
| -rw-r--r-- | kernel/rtlil.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 81ca93dce..8509670ff 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -601,6 +601,7 @@ struct RTLIL::SigChunk RTLIL::SigChunk &operator =(const RTLIL::SigChunk &other) = default; RTLIL::SigChunk extract(int offset, int length) const; + inline int size() const { return width; } bool operator <(const RTLIL::SigChunk &other) const; bool operator ==(const RTLIL::SigChunk &other) const; |