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author | Clifford Wolf <clifford@clifford.at> | 2019-04-23 22:57:10 +0200 |
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committer | Clifford Wolf <clifford@clifford.at> | 2019-04-23 22:57:10 +0200 |
commit | 64925b4e8f7890f5447d9655b2c69dd59a93f7cd (patch) | |
tree | 393ed31a9228a475077864ef5419412d1910212b /kernel | |
parent | 4575e4ad86494e99dd05200f7242dfa632053c78 (diff) | |
download | yosys-64925b4e8f7890f5447d9655b2c69dd59a93f7cd.tar.gz yosys-64925b4e8f7890f5447d9655b2c69dd59a93f7cd.tar.bz2 yosys-64925b4e8f7890f5447d9655b2c69dd59a93f7cd.zip |
Improve $specrule interface
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Diffstat (limited to 'kernel')
-rw-r--r-- | kernel/rtlil.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 3dd18c296..040644c47 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -1219,13 +1219,13 @@ namespace { } if (cell->type == "$specrule") { + param("\\TYPE"); param_bool("\\SRC_PEN"); param_bool("\\SRC_POL"); param_bool("\\DST_PEN"); param_bool("\\DST_POL"); - param_bool("\\SKEW"); - param_bool("\\HOLD"); param("\\T_LIMIT"); + param("\\T_LIMIT2"); port("\\SRC_EN", 1); port("\\DST_EN", 1); port("\\SRC", param("\\SRC_WIDTH")); |