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author | Clifford Wolf <clifford@clifford.at> | 2019-06-20 13:04:04 +0200 |
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committer | Clifford Wolf <clifford@clifford.at> | 2019-06-20 13:04:04 +0200 |
commit | 73bd1d59a7579ea74fb4a201771c983eeaf9a76a (patch) | |
tree | 831ca8451498c91da804c4e4da33af12728b1589 /kernel | |
parent | 11ec7b2aecddc72747ccdc30d2674583062d58d3 (diff) | |
parent | 8451cbea896d2b441b5c78eb2813790616d10b84 (diff) | |
download | yosys-73bd1d59a7579ea74fb4a201771c983eeaf9a76a.tar.gz yosys-73bd1d59a7579ea74fb4a201771c983eeaf9a76a.tar.bz2 yosys-73bd1d59a7579ea74fb4a201771c983eeaf9a76a.zip |
Merge branch 'master' of https://github.com/bogdanvuk/yosys into clifford/ext1046
Diffstat (limited to 'kernel')
-rw-r--r-- | kernel/celltypes.h | 9 |
1 files changed, 4 insertions, 5 deletions
diff --git a/kernel/celltypes.h b/kernel/celltypes.h index 4e91eddda..758661c02 100644 --- a/kernel/celltypes.h +++ b/kernel/celltypes.h @@ -246,24 +246,24 @@ struct CellTypes cell_types.clear(); } - bool cell_known(RTLIL::IdString type) + bool cell_known(RTLIL::IdString type) const { return cell_types.count(type) != 0; } - bool cell_output(RTLIL::IdString type, RTLIL::IdString port) + bool cell_output(RTLIL::IdString type, RTLIL::IdString port) const { auto it = cell_types.find(type); return it != cell_types.end() && it->second.outputs.count(port) != 0; } - bool cell_input(RTLIL::IdString type, RTLIL::IdString port) + bool cell_input(RTLIL::IdString type, RTLIL::IdString port) const { auto it = cell_types.find(type); return it != cell_types.end() && it->second.inputs.count(port) != 0; } - bool cell_evaluable(RTLIL::IdString type) + bool cell_evaluable(RTLIL::IdString type) const { auto it = cell_types.find(type); return it != cell_types.end() && it->second.is_evaluable; @@ -482,4 +482,3 @@ extern CellTypes yosys_celltypes; YOSYS_NAMESPACE_END #endif - |