| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | Replaced RTLIL::SigSpec::operator!=() with inline version | Clifford Wolf | 2014-07-23 | 2 | -8/+1 |
| * | Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3 | Clifford Wolf | 2014-07-23 | 3 | -22/+14 |
| * | Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 2/3 | Clifford Wolf | 2014-07-23 | 2 | -18/+4 |
| * | Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 1/3 | Clifford Wolf | 2014-07-23 | 2 | -2/+40 |
| * | Some cleanups in RTLIL::SigChunk::SigChunk(const RTLIL::Const&) | Clifford Wolf | 2014-07-23 | 2 | -6/+6 |
| * | SigSpec refactoring: More cleanups of old SigSpec use pattern | Clifford Wolf | 2014-07-22 | 2 | -55/+50 |
| * | SigSpec refactoring: Added RTLIL::SigSpecIterator | Clifford Wolf | 2014-07-22 | 1 | -6/+28 |
| * | SigSpec refactoring: added RTLIL::SigSpec::operator[] | Clifford Wolf | 2014-07-22 | 1 | -1/+4 |
| * | SigSpec refactoring: rewrote some RTLIL::SigSpec methods to use unpacked form | Clifford Wolf | 2014-07-22 | 1 | -182/+113 |
| * | Removed RTLIL::SigChunk::compare() | Clifford Wolf | 2014-07-22 | 2 | -25/+5 |
| * | SigSpec refactoring: added RTLIL::SigSpec::bits() and pack/unpack api | Clifford Wolf | 2014-07-22 | 2 | -18/+135 |
| * | SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created... | Clifford Wolf | 2014-07-22 | 4 | -7/+7 |
| * | SigSpec refactoring: change RTLIL::SigSpec::size() to be read-only | Clifford Wolf | 2014-07-22 | 1 | -2/+1 |
| * | SigSpec refactoring: using the accessor functions everywhere | Clifford Wolf | 2014-07-22 | 6 | -93/+93 |
| * | SigSpec refactoring: renamed the SigSpec members to chunks_ and width_ and ad... | Clifford Wolf | 2014-07-22 | 2 | -152/+158 |
| * | SigSpec refactoring: renamed chunks and width to __chunks and __width | Clifford Wolf | 2014-07-22 | 6 | -244/+247 |
| * | Added support for scripts with labels | Clifford Wolf | 2014-07-21 | 1 | -11/+74 |
| * | Replaced depricated NEW_WIRE macro with module->addWire() calls | Clifford Wolf | 2014-07-21 | 1 | -3/+0 |
| * | Removed deprecated module->new_wire() | Clifford Wolf | 2014-07-21 | 2 | -20/+11 |
| * | Bugfix in satgen for cells with wider in- than outputs. | Clifford Wolf | 2014-07-21 | 1 | -1/+9 |
| * | Added module->remove(), module->addWire(), module->addCell(), cell->check() | Clifford Wolf | 2014-07-21 | 2 | -8/+44 |
| * | Added log_ping() | Clifford Wolf | 2014-07-21 | 1 | -0/+1 |
| * | Added call_on_selection() and call_on_module() API | Clifford Wolf | 2014-07-20 | 2 | -6/+35 |
| * | Added std::set<RTLIL::SigBit> to RTLIL::SigSpec conversion | Clifford Wolf | 2014-07-20 | 2 | -3/+11 |
| * | Added SIZE() macro | Clifford Wolf | 2014-07-20 | 1 | -0/+2 |
| * | Added log_cell() | Clifford Wolf | 2014-07-20 | 2 | -0/+17 |
| * | Fixed log_id() memory corruption | Clifford Wolf | 2014-07-19 | 2 | -5/+10 |
| * | Added ModWalker helper class | Clifford Wolf | 2014-07-19 | 1 | -0/+298 |
| * | Some "const" cleanups in SigMap | Clifford Wolf | 2014-07-19 | 1 | -4/+4 |
| * | Added automatic conversion from RTLIL::SigSpec to std::vector<RTLIL::SigBit> | Clifford Wolf | 2014-07-18 | 1 | -0/+1 |
| * | Added function-like cell creation helpers | Clifford Wolf | 2014-07-18 | 2 | -73/+158 |
| * | Added log_id() helper function | Clifford Wolf | 2014-07-18 | 1 | -0/+8 |
| * | Fixed RTLIL::SigSpec::append_bit() for appending constants | Clifford Wolf | 2014-07-17 | 1 | -2/+3 |
| * | Changed the $mem/$memwr WR_EN input to a per-data-bit enable signal | Clifford Wolf | 2014-07-16 | 1 | -2/+2 |
| * | Use "verilog -sv" to parse .sv files | Clifford Wolf | 2014-07-11 | 1 | -0/+2 |
| * | Add support for cell arrays | Clifford Wolf | 2014-06-07 | 1 | -1/+2 |
| * | Improved error message for options after front-end filename arguments | Clifford Wolf | 2014-06-04 | 1 | -0/+4 |
| * | workaround for OpenBSD 'stdout' implementation | Clifford Wolf | 2014-05-03 | 1 | -1/+2 |
| * | workaround for OpenBSD 'stdin' implementation | Clifford Wolf | 2014-05-02 | 1 | -1/+2 |
| * | Added support for dlatchsr cells | Clifford Wolf | 2014-03-31 | 3 | -1/+71 |
| * | Fixed typo in RTLIL::Module::addAdff() | Clifford Wolf | 2014-03-17 | 1 | -1/+1 |
| * | Fixed typo in RTLIL::Module::{addSshl,addSshr} | Clifford Wolf | 2014-03-15 | 1 | -2/+2 |
| * | Added RTLIL::Module::add{Dff,Dffsr,Adff,Dlatch}Gate() API | Clifford Wolf | 2014-03-15 | 2 | -1/+61 |
| * | Added log_dump() support for generic pointers | Clifford Wolf | 2014-03-14 | 1 | -0/+3 |
| * | Progress in Verific bindings | Clifford Wolf | 2014-03-14 | 1 | -1/+1 |
| * | Added RTLIL::Module::Add{Inv,And,Or,Xor,Mux}Gate API | Clifford Wolf | 2014-03-14 | 2 | -0/+48 |
| * | Hotfix for kernel/compatibility.h | Clifford Wolf | 2014-03-13 | 1 | -1/+2 |
| * | Merged OSX fixes from Siesh1oo with some modifications | Clifford Wolf | 2014-03-13 | 5 | -2/+176 |
| * | - kernel/register.h, kernel/driver.cc: refactor rewrite_yosys_exe()/get_shar... | Siesh1oo | 2014-03-12 | 2 | -34/+39 |
| * | Added libs/minisat (copy of minisat git master) | Clifford Wolf | 2014-03-12 | 1 | -6/+1 |
