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| author | Clifford Wolf <clifford@clifford.at> | 2014-07-20 11:00:09 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-07-20 11:01:04 +0200 |
| commit | e57db5e9b256d801c1d4337e44e1a7173a115d07 (patch) | |
| tree | 9b4dfae20d2b1fce65fa320354c5d626a0678963 /kernel | |
| parent | efa78840261871616f9af15e5ad9a5bc89f95857 (diff) | |
| download | yosys-e57db5e9b256d801c1d4337e44e1a7173a115d07.tar.gz yosys-e57db5e9b256d801c1d4337e44e1a7173a115d07.tar.bz2 yosys-e57db5e9b256d801c1d4337e44e1a7173a115d07.zip | |
Added std::set<RTLIL::SigBit> to RTLIL::SigSpec conversion
Diffstat (limited to 'kernel')
| -rw-r--r-- | kernel/rtlil.cc | 13 | ||||
| -rw-r--r-- | kernel/rtlil.h | 1 |
2 files changed, 11 insertions, 3 deletions
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index dea0e1050..748deae3e 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -1451,10 +1451,17 @@ RTLIL::SigSpec::SigSpec(RTLIL::SigBit bit, int width) RTLIL::SigSpec::SigSpec(std::vector<RTLIL::SigBit> bits) { - chunks.reserve(bits.size()); + this->width = 0; for (auto &bit : bits) - chunks.push_back(bit); - this->width = bits.size(); + append_bit(bit); + check(); +} + +RTLIL::SigSpec::SigSpec(std::set<RTLIL::SigBit> bits) +{ + this->width = 0; + for (auto &bit : bits) + append_bit(bit); check(); } diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 6290db21d..64136de04 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -505,6 +505,7 @@ struct RTLIL::SigSpec { SigSpec(RTLIL::State bit, int width = 1); SigSpec(RTLIL::SigBit bit, int width = 1); SigSpec(std::vector<RTLIL::SigBit> bits); + SigSpec(std::set<RTLIL::SigBit> bits); void expand(); void optimize(); RTLIL::SigSpec optimized() const; |