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author | Clifford Wolf <clifford@clifford.at> | 2014-07-22 22:54:03 +0200 |
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committer | Clifford Wolf <clifford@clifford.at> | 2014-07-22 22:54:03 +0200 |
commit | f80da7b41dd9c12d3bd65ceab6c0c6748a70a78c (patch) | |
tree | 30213162e8e1bcc1d53c2b1b4ed27bb15352a4d5 /kernel | |
parent | e7e30f1c86d978131a5f4c6e62b5b8d822696cd1 (diff) | |
download | yosys-f80da7b41dd9c12d3bd65ceab6c0c6748a70a78c.tar.gz yosys-f80da7b41dd9c12d3bd65ceab6c0c6748a70a78c.tar.bz2 yosys-f80da7b41dd9c12d3bd65ceab6c0c6748a70a78c.zip |
SigSpec refactoring: added RTLIL::SigSpec::operator[]
Diffstat (limited to 'kernel')
-rw-r--r-- | kernel/rtlil.h | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/kernel/rtlil.h b/kernel/rtlil.h index facd43db4..da3a2661e 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -522,6 +522,9 @@ public: int size() const { return width_; } + RTLIL::SigBit &operator[](int index) { unpack(); return bits_.at(index); } + const RTLIL::SigBit &operator[](int index) const { unpack(); return bits_.at(index); } + void expand(); void optimize(); RTLIL::SigSpec optimized() const; @@ -540,7 +543,7 @@ public: void remove_const(); RTLIL::SigSpec extract(RTLIL::SigSpec pattern, RTLIL::SigSpec *other = NULL) const; - RTLIL::SigSpec extract(int offset, int length) const; + RTLIL::SigSpec extract(int offset, int length = 1) const; void append(const RTLIL::SigSpec &signal); void append_bit(const RTLIL::SigBit &bit); |