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| author | Clifford Wolf <clifford@clifford.at> | 2014-03-17 14:41:41 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-03-17 14:41:41 +0100 |
| commit | e164edc8d11356c0999c44dfdb52d0b2b337f212 (patch) | |
| tree | b95f89eb633efef28982719df2eab5aab4989e30 /kernel | |
| parent | 0b0dcfda7d6a860713e67f3a0c50f6636be687d5 (diff) | |
| download | yosys-e164edc8d11356c0999c44dfdb52d0b2b337f212.tar.gz yosys-e164edc8d11356c0999c44dfdb52d0b2b337f212.tar.bz2 yosys-e164edc8d11356c0999c44dfdb52d0b2b337f212.zip | |
Fixed typo in RTLIL::Module::addAdff()
Diffstat (limited to 'kernel')
| -rw-r--r-- | kernel/rtlil.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 2b28f3232..1d53bc79b 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -1096,7 +1096,7 @@ RTLIL::Cell* RTLIL::Module::addAdff(RTLIL::IdString name, RTLIL::SigSpec sig_clk { RTLIL::Cell *cell = new RTLIL::Cell; cell->name = name; - cell->type = "$dffsr"; + cell->type = "$adff"; cell->parameters["\\CLK_POLARITY"] = clk_polarity; cell->parameters["\\ARST_POLARITY"] = arst_polarity; cell->parameters["\\ARST_VALUE"] = arst_value; |