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| author | Clifford Wolf <clifford@clifford.at> | 2014-07-16 11:38:02 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-07-16 11:38:02 +0200 |
| commit | 73e0e13d2f1b959a05d69ed715c8fdde84894d6f (patch) | |
| tree | 8a604b9990ca8e3ffd405b5e74a2d0e01141fb4b /kernel | |
| parent | 964a67ac4194bb85fb3cb7a90a62dc1e4a685ea4 (diff) | |
| download | yosys-73e0e13d2f1b959a05d69ed715c8fdde84894d6f.tar.gz yosys-73e0e13d2f1b959a05d69ed715c8fdde84894d6f.tar.bz2 yosys-73e0e13d2f1b959a05d69ed715c8fdde84894d6f.zip | |
Changed the $mem/$memwr WR_EN input to a per-data-bit enable signal
Diffstat (limited to 'kernel')
| -rw-r--r-- | kernel/rtlil.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 028cd6d81..c4c08d5b8 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -619,7 +619,7 @@ namespace { param_bool("\\CLK_POLARITY"); param("\\PRIORITY"); port("\\CLK", 1); - port("\\EN", 1); + port("\\EN", param("\\WIDTH")); port("\\ADDR", param("\\ABITS")); port("\\DATA", param("\\WIDTH")); check_expected(); @@ -639,7 +639,7 @@ namespace { port("\\RD_ADDR", param("\\RD_PORTS") * param("\\ABITS")); port("\\RD_DATA", param("\\RD_PORTS") * param("\\WIDTH")); port("\\WR_CLK", param("\\WR_PORTS")); - port("\\WR_EN", param("\\WR_PORTS")); + port("\\WR_EN", param("\\WR_PORTS") * param("\\WIDTH")); port("\\WR_ADDR", param("\\WR_PORTS") * param("\\ABITS")); port("\\WR_DATA", param("\\WR_PORTS") * param("\\WIDTH")); check_expected(); |