aboutsummaryrefslogtreecommitdiffstats
path: root/kernel/satgen.h
Commit message (Expand)AuthorAgeFilesLines
* kernel: big fat patch to use more ID::*, otherwise ID(*)Eddie Hung2020-04-021-56/+56
* Use more ID::{A,B,Y,blackbox,whitebox}Eddie Hung2019-08-151-118/+118
* More use of IdString::in()Eddie Hung2019-08-151-26/+25
* Use ID() in kernel/*, add simple ID:: hack (to be improved upon later)Clifford Wolf2019-08-111-261/+261
* RTLIL::S{0,1} -> State::S{0,1} for headersEddie Hung2019-08-071-1/+1
* Add $_NMUX_, add "abc -g cmos", add proper cmos cell costsClifford Wolf2019-08-061-2/+5
* Consistent use of 'override' for virtual methods in derived classes.Henner Zeller2018-07-201-1/+1
* Add $_ANDNOT_ and $_ORNOT_ gatesClifford Wolf2017-05-171-1/+18
* Fix undef propagation bug in $pmux SAT modelClifford Wolf2017-02-051-14/+4
* Added $anyseq cell typeClifford Wolf2016-10-141-2/+7
* Added $ff and $_FF_ cell typesClifford Wolf2016-10-121-1/+1
* Added SatGen support for $anyconstClifford Wolf2016-07-271-0/+22
* Removed $predict support from SatGenClifford Wolf2016-07-271-9/+0
* Added satgen initstate supportClifford Wolf2016-07-221-0/+27
* Added $initstate cell type and vlog functionClifford Wolf2016-07-211-3/+3
* After reading the SV spec, using non-standard predict() instead of expect()Clifford Wolf2016-07-211-1/+1
* Added basic support for $expect cellsClifford Wolf2016-07-131-0/+9
* Added $sop SAT modelClifford Wolf2016-06-171-0/+82
* Import more std:: stuff into Yosys namespaceClifford Wolf2015-10-251-1/+1
* Fixed trailing whitespacesClifford Wolf2015-07-021-2/+2
* Added $assume cell typeClifford Wolf2015-02-261-0/+30
* Replaced ezDefaultSAT with ezSatPtrClifford Wolf2015-02-211-1/+31
* Added "equiv_simple -undef"Clifford Wolf2015-01-311-0/+14
* Various equiv_simple improvementsClifford Wolf2015-01-221-0/+19
* Fixed a few VS warningsClifford Wolf2014-10-171-1/+1
* Added format __attribute__ to stringf()Clifford Wolf2014-10-101-1/+1
* Renamed TRUE/FALSE to CONST_TRUE/CONST_FALSE because of name collision on Win32Clifford Wolf2014-10-101-52/+52
* Renamed SIZE() to GetSize() because of name collision on Win32Clifford Wolf2014-10-101-32/+32
* satgen import sigbit apiClifford Wolf2014-10-031-1/+17
* namespace YosysClifford Wolf2014-09-271-0/+5
* Simplified $fa undef modelClifford Wolf2014-09-081-14/+1
* Added $lcu cell typeClifford Wolf2014-09-081-0/+32
* Added "$fa" cell typeClifford Wolf2014-09-081-0/+49
* Added $macc SAT modelClifford Wolf2014-09-061-0/+71
* Removed $bu0 cell typeClifford Wolf2014-09-041-3/+3
* Using $pos models for $bu0Clifford Wolf2014-09-031-1/+1
* Fixes in $alu SAT- and eval-modelsClifford Wolf2014-09-031-4/+3
* Small bug fixes in $not, $neg, and $shiftx modelsClifford Wolf2014-09-021-3/+4
* Added SAT model for $alu cellsClifford Wolf2014-09-011-2/+69
* Added $lut support in test_cell, techmap, satgenClifford Wolf2014-08-311-1/+50
* Added additional gate types: $_NAND_ $_NOR_ $_XNOR_ $_AOI3_ $_OAI3_ $_AOI4_ $...Clifford Wolf2014-08-161-7/+81
* Renamed $_INV_ cell type to $_NOT_Clifford Wolf2014-08-151-1/+1
* RIP $safe_pmuxClifford Wolf2014-08-141-9/+1
* Renamed port access function on RTLIL::Cell, added param access functionsClifford Wolf2014-07-311-85/+85
* Using native ezSAT shift ops in satgen, fixed $shift and $shiftx SAT modelsClifford Wolf2014-07-301-36/+39
* Added $shift and $shiftx cell types (needed for correct part select behavior)Clifford Wolf2014-07-291-4/+14
* Using log_assert() instead of assert()Clifford Wolf2014-07-281-4/+4
* Changed users of cell->connections_ to the new API (sed command)Clifford Wolf2014-07-261-85/+85
* Renamed RTLIL::{Module,Cell}::connections to connections_Clifford Wolf2014-07-261-85/+85
* Removed RTLIL::SigSpec::expand() methodClifford Wolf2014-07-231-6/+4