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| author | Clifford Wolf <clifford@clifford.at> | 2016-07-21 14:23:22 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2016-07-21 14:23:22 +0200 |
| commit | 5c166e76e52cdaf6ea97952c17d3d79185a59f96 (patch) | |
| tree | e0f790a82816d5a148eb913b00176f4a581f5464 /kernel/satgen.h | |
| parent | d7763634b68a735443c61aa32918ee0cdd6e9250 (diff) | |
| download | yosys-5c166e76e52cdaf6ea97952c17d3d79185a59f96.tar.gz yosys-5c166e76e52cdaf6ea97952c17d3d79185a59f96.tar.bz2 yosys-5c166e76e52cdaf6ea97952c17d3d79185a59f96.zip | |
Added $initstate cell type and vlog function
Diffstat (limited to 'kernel/satgen.h')
| -rw-r--r-- | kernel/satgen.h | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/kernel/satgen.h b/kernel/satgen.h index 22b11fe26..eb1c6fe36 100644 --- a/kernel/satgen.h +++ b/kernel/satgen.h @@ -69,7 +69,7 @@ struct SatGen SigPool initial_state; std::map<std::string, RTLIL::SigSpec> asserts_a, asserts_en; std::map<std::string, RTLIL::SigSpec> assumes_a, assumes_en; - std::map<std::string, RTLIL::SigSpec> expects_a, expects_en; + std::map<std::string, RTLIL::SigSpec> predict_a, predict_en; std::map<std::string, std::map<RTLIL::SigBit, int>> imported_signals; bool ignore_div_by_zero; bool model_undef; @@ -1350,8 +1350,8 @@ struct SatGen if (cell->type == "$predict") { std::string pf = prefix + (timestep == -1 ? "" : stringf("@%d:", timestep)); - expects_a[pf].append((*sigmap)(cell->getPort("\\A"))); - expects_en[pf].append((*sigmap)(cell->getPort("\\EN"))); + predict_a[pf].append((*sigmap)(cell->getPort("\\A"))); + predict_en[pf].append((*sigmap)(cell->getPort("\\EN"))); return true; } |