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| author | Clifford Wolf <clifford@clifford.at> | 2016-07-13 16:56:17 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2016-07-13 16:56:17 +0200 |
| commit | 721f1f5ecfb6334904f6058d6d376d21b5efc438 (patch) | |
| tree | 3573f744b6d7c33f55dd06a152d4ff199cf30b22 /kernel/satgen.h | |
| parent | b3155af5f65333d272da339222e1e1962fb088b7 (diff) | |
| download | yosys-721f1f5ecfb6334904f6058d6d376d21b5efc438.tar.gz yosys-721f1f5ecfb6334904f6058d6d376d21b5efc438.tar.bz2 yosys-721f1f5ecfb6334904f6058d6d376d21b5efc438.zip | |
Added basic support for $expect cells
Diffstat (limited to 'kernel/satgen.h')
| -rw-r--r-- | kernel/satgen.h | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/kernel/satgen.h b/kernel/satgen.h index e118c1569..da892c710 100644 --- a/kernel/satgen.h +++ b/kernel/satgen.h @@ -69,6 +69,7 @@ struct SatGen SigPool initial_state; std::map<std::string, RTLIL::SigSpec> asserts_a, asserts_en; std::map<std::string, RTLIL::SigSpec> assumes_a, assumes_en; + std::map<std::string, RTLIL::SigSpec> expects_a, expects_en; std::map<std::string, std::map<RTLIL::SigBit, int>> imported_signals; bool ignore_div_by_zero; bool model_undef; @@ -1346,6 +1347,14 @@ struct SatGen return true; } + if (cell->type == "$expect") + { + std::string pf = prefix + (timestep == -1 ? "" : stringf("@%d:", timestep)); + expects_a[pf].append((*sigmap)(cell->getPort("\\A"))); + expects_en[pf].append((*sigmap)(cell->getPort("\\EN"))); + return true; + } + // Unsupported internal cell types: $pow $lut // .. and all sequential cells except $dff and $_DFF_[NP]_ return false; |