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| author | Clifford Wolf <clifford@clifford.at> | 2014-10-17 06:02:38 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-10-17 06:02:38 +0200 |
| commit | 34caeeb4f3e21d8da3b75682e48ab85c27021b82 (patch) | |
| tree | 4515ce4d39e8b9ad0c22865ab682714616f246d0 /kernel/satgen.h | |
| parent | 18cb8b4636933cb5a1ad3040f061d53345d1aa1d (diff) | |
| download | yosys-34caeeb4f3e21d8da3b75682e48ab85c27021b82.tar.gz yosys-34caeeb4f3e21d8da3b75682e48ab85c27021b82.tar.bz2 yosys-34caeeb4f3e21d8da3b75682e48ab85c27021b82.zip | |
Fixed a few VS warnings
Diffstat (limited to 'kernel/satgen.h')
| -rw-r--r-- | kernel/satgen.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/kernel/satgen.h b/kernel/satgen.h index d556f4f32..2c69663c4 100644 --- a/kernel/satgen.h +++ b/kernel/satgen.h @@ -107,7 +107,7 @@ struct SatGen { log_assert(timestep != 0); std::string pf = prefix + (timestep == -1 ? "" : stringf("@%d:", timestep)); - return imported_signals[pf].count(bit); + return imported_signals[pf].count(bit) != 0; } void getAsserts(RTLIL::SigSpec &sig_a, RTLIL::SigSpec &sig_en, int timestep = -1) |