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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-07 11:14:03 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-07 11:14:03 -0700 |
| commit | 71eff6f0deae3ffaf75cca22768b66a2dc918b3e (patch) | |
| tree | 7bc05d412a20985e701abc2607bd2d682c5fcb83 /kernel/satgen.h | |
| parent | 71649969213863b2695f1c51956886fc7879c3e6 (diff) | |
| download | yosys-71eff6f0deae3ffaf75cca22768b66a2dc918b3e.tar.gz yosys-71eff6f0deae3ffaf75cca22768b66a2dc918b3e.tar.bz2 yosys-71eff6f0deae3ffaf75cca22768b66a2dc918b3e.zip | |
RTLIL::S{0,1} -> State::S{0,1} for headers
Diffstat (limited to 'kernel/satgen.h')
| -rw-r--r-- | kernel/satgen.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/kernel/satgen.h b/kernel/satgen.h index e9f3ecd44..596f522ec 100644 --- a/kernel/satgen.h +++ b/kernel/satgen.h @@ -1023,7 +1023,7 @@ struct SatGen std::vector<int> lut; for (auto bit : cell->getParam("\\LUT").bits) - lut.push_back(bit == RTLIL::S1 ? ez->CONST_TRUE : ez->CONST_FALSE); + lut.push_back(bit == State::S1 ? ez->CONST_TRUE : ez->CONST_FALSE); while (GetSize(lut) < (1 << GetSize(a))) lut.push_back(ez->CONST_FALSE); lut.resize(1 << GetSize(a)); |