| Commit message (Expand) | Author | Age | Files | Lines |
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| * | add IdString::isPublic() | N. Engelhardt | 2020-09-03 | 1 | -0/+2 |
| * | Add add* functions for the new FF types | Marcelina Kościelnicka | 2020-06-23 | 1 | -0/+20 |
| * | Merge pull request #2177 from boqwxp/dict-iterator-jump | whitequark | 2020-06-21 | 1 | -0/+23 |
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| | * | hashlib, rtlil: Add `operator+=()` to `dict<>::iterator` and `dict<>::const_i... | Alberto Gonzalez | 2020-06-19 | 1 | -0/+23 |
| * | | rtlil: Add `Design::select()` for selecting whole modules. | Alberto Gonzalez | 2020-06-19 | 1 | -0/+7 |
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| * | RTLIL: add Module::addProcess, use it in Module::cloneInto. NFC. | whitequark | 2020-06-09 | 1 | -0/+2 |
| * | flatten: preserve original object names via hdlname attribute. | whitequark | 2020-06-08 | 1 | -0/+3 |
| * | Merge pull request #2105 from whitequark/split-flatten-off-techmap | clairexen | 2020-06-08 | 1 | -0/+2 |
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| | * | RTLIL: factor out RTLIL::Module::addMemory. NFC. | whitequark | 2020-06-04 | 1 | -0/+2 |
| * | | Merge pull request #2006 from jersey99/signed-in-rtlil-wire | whitequark | 2020-06-04 | 1 | -1/+1 |
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| | * | | Preserve 'signed'-ness of a verilog wire through RTLIL | Vamsi K Vytla | 2020-04-27 | 1 | -1/+1 |
| * | | | Merge pull request #2070 from hackfin/master | N. Engelhardt | 2020-06-04 | 1 | -6/+3 |
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| | * | | idict handling in wrapper | Martin | 2020-05-19 | 1 | -6/+3 |
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| * | | Merge pull request #1885 from Xiretza/mod-rem-cells | clairexen | 2020-05-29 | 1 | -0/+10 |
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| | * | | Add comments for mod/div semantics to rtlil.h | Xiretza | 2020-05-28 | 1 | -0/+4 |
| | * | | Add flooring division operator | Xiretza | 2020-05-28 | 1 | -0/+3 |
| | * | | Add flooring modulo operator | Xiretza | 2020-05-28 | 1 | -0/+3 |
| * | | | Merge pull request #2092 from whitequark/rtlil-no-space-control | clairexen | 2020-05-29 | 1 | -3/+5 |
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| | * | | Restrict RTLIL::IdString to not contain whitespace or control chars. | whitequark | 2020-05-29 | 1 | -3/+5 |
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| * | | Merge pull request #2088 from rswarbrick/count-at | whitequark | 2020-05-28 | 1 | -2/+8 |
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| | * | | Minor optimisation in Module::wire() and Module::cell() | Rupert Swarbrick | 2020-05-26 | 1 | -2/+8 |
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| * | | Merge pull request #2086 from rswarbrick/sigbit | whitequark | 2020-05-28 | 1 | -2/+1 |
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| | * | | Use default copy constructor for RTLIL::SigBit | Rupert Swarbrick | 2020-05-26 | 1 | -2/+1 |
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| * / | Use c_str(), not str() for IdString/std::string == and != operators | Rupert Swarbrick | 2020-05-26 | 1 | -2/+2 |
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| * | ilang, ast: Store parameter order and default value information. | Marcelina Kościelnicka | 2020-04-21 | 1 | -1/+2 |
| * | rtlil: add AttrObject::has_attribute. | whitequark | 2020-04-16 | 1 | -0/+2 |
| * | rtlil: add AttrObject::{get,set}_string_attribute. | whitequark | 2020-04-16 | 1 | -2/+9 |
| * | Merge pull request #1858 from YosysHQ/eddie/fix1856 | Eddie Hung | 2020-04-09 | 1 | -1/+1 |
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| | * | kernel: include "kernel/constids.inc" instead of "constids.inc" | Eddie Hung | 2020-04-09 | 1 | -1/+1 |
| * | | [NFCI] Deduplicate builtin FF cell types list | Marcelina Kościelnicka | 2020-04-09 | 1 | -0/+2 |
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| * | kernel: IdString::in(const IdString &) as per @Tjoppen | Eddie Hung | 2020-04-02 | 1 | -1/+1 |
| * | kernel: fix formatting (thanks @boqwxp) | Eddie Hung | 2020-04-02 | 1 | -6/+4 |
| * | kernel: use C++11 fold hack to prevent recursion | Eddie Hung | 2020-04-02 | 1 | -3/+8 |
| * | Revert "kernel: IdString:in() to use perfect forwarding" | Eddie Hung | 2020-04-02 | 1 | -2/+2 |
| * | kernel: separate IdString::put_reference() out to help inlining | Eddie Hung | 2020-04-02 | 1 | -1/+4 |
| * | kernel: IdString:in() to use perfect forwarding | Eddie Hung | 2020-04-02 | 1 | -2/+2 |
| * | kernel: Use constids.inc for global/constant IdStrings | Eddie Hung | 2020-04-02 | 1 | -5/+3 |
| * | Merge pull request #1845 from YosysHQ/eddie/kernel_speedup | Eddie Hung | 2020-04-02 | 1 | -181/+191 |
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| | * | kernel: pass-by-value into Design::scratchpad_set_string() too | Eddie Hung | 2020-03-27 | 1 | -1/+1 |
| | * | kernel: Cell::set{Port,Param}() to pass by value, but use std::move | Eddie Hung | 2020-03-26 | 1 | -2/+2 |
| | * | kernel: SigSpec copies to not trigger pack() | Eddie Hung | 2020-03-18 | 1 | -1/+1 |
| | * | kernel: more pass by const ref, more speedups | Eddie Hung | 2020-03-18 | 1 | -180/+180 |
| | * | kernel: SigSpec use more const& + overloads to prevent implicit SigSpec | Eddie Hung | 2020-03-13 | 1 | -7/+13 |
| | * | kernel: optimise Module::remove(const pool<RTLIL::Wire*>() | Eddie Hung | 2020-03-12 | 1 | -0/+4 |
| * | | Add support for SystemVerilog-style `define to Verilog frontend | Rupert Swarbrick | 2020-03-27 | 1 | -1/+4 |
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| * | Add and use SigSpec::reverse() | Eddie Hung | 2020-01-28 | 1 | -0/+2 |
| * | Add RTLIL::constpad, init by yosys_setup(); use for abc9 | Eddie Hung | 2020-01-08 | 1 | -0/+2 |
| * | Add Const::{begin,end,empty}() | Eddie Hung | 2019-10-04 | 1 | -0/+3 |
| * | Add YOSYS_NO_IDS_REFCNT configuration macro | Clifford Wolf | 2019-08-11 | 1 | -1/+22 |
| * | Use ID() in kernel/*, add simple ID:: hack (to be improved upon later) | Clifford Wolf | 2019-08-11 | 1 | -3/+11 |
