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| author | whitequark <whitequark@whitequark.org> | 2020-06-03 14:35:27 +0000 |
|---|---|---|
| committer | whitequark <whitequark@whitequark.org> | 2020-06-04 00:02:12 +0000 |
| commit | 9338ff66b9fb86f3485f060b04f4e4b8a1fc18f6 (patch) | |
| tree | c3ef5451736051cfb441f801168944449ce940aa /kernel/rtlil.h | |
| parent | ebbbe2156e9c5f2d04964840974c915ba8500159 (diff) | |
| download | yosys-9338ff66b9fb86f3485f060b04f4e4b8a1fc18f6.tar.gz yosys-9338ff66b9fb86f3485f060b04f4e4b8a1fc18f6.tar.bz2 yosys-9338ff66b9fb86f3485f060b04f4e4b8a1fc18f6.zip | |
RTLIL: factor out RTLIL::Module::addMemory. NFC.
Diffstat (limited to 'kernel/rtlil.h')
| -rw-r--r-- | kernel/rtlil.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 8228523d5..8d2e42b42 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -1170,6 +1170,8 @@ public: RTLIL::Cell *addCell(RTLIL::IdString name, RTLIL::IdString type); RTLIL::Cell *addCell(RTLIL::IdString name, const RTLIL::Cell *other); + RTLIL::Memory *addMemory(RTLIL::IdString name, const RTLIL::Memory *other); + // The add* methods create a cell and return the created cell. All signals must exist in advance. RTLIL::Cell* addNot (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = ""); |