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| author | Eddie Hung <eddie@fpgeh.com> | 2020-01-28 10:37:16 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-01-28 10:37:16 -0800 |
| commit | 6d27d4372730cb94306a4f314482459f9d527d7c (patch) | |
| tree | 1d1ed19e628d8bb17c48c2b100d525d7bc05672e /kernel/rtlil.h | |
| parent | e18aeda7ed3b3dbf4700e25c2bc745c93541b3b8 (diff) | |
| download | yosys-6d27d4372730cb94306a4f314482459f9d527d7c.tar.gz yosys-6d27d4372730cb94306a4f314482459f9d527d7c.tar.bz2 yosys-6d27d4372730cb94306a4f314482459f9d527d7c.zip | |
Add and use SigSpec::reverse()
Diffstat (limited to 'kernel/rtlil.h')
| -rw-r--r-- | kernel/rtlil.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 6251d265d..58c5d9674 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -851,6 +851,8 @@ public: RTLIL::SigSpec repeat(int num) const; + void reverse() { inline_unpack(); std::reverse(bits_.begin(), bits_.end()); } + bool operator <(const RTLIL::SigSpec &other) const; bool operator ==(const RTLIL::SigSpec &other) const; inline bool operator !=(const RTLIL::SigSpec &other) const { return !(*this == other); } |