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| author | whitequark <whitequark@whitequark.org> | 2020-06-09 09:55:48 +0000 |
|---|---|---|
| committer | whitequark <whitequark@whitequark.org> | 2020-06-09 09:55:48 +0000 |
| commit | 483a1081e7587f8b3bee6d56fb4e577a97281fbe (patch) | |
| tree | 719987ff619479b0029928fb66f5899f05d1737e /kernel/rtlil.h | |
| parent | 74e3ac2449f521a50d5e88daa951acee1062e620 (diff) | |
| download | yosys-483a1081e7587f8b3bee6d56fb4e577a97281fbe.tar.gz yosys-483a1081e7587f8b3bee6d56fb4e577a97281fbe.tar.bz2 yosys-483a1081e7587f8b3bee6d56fb4e577a97281fbe.zip | |
RTLIL: add Module::addProcess, use it in Module::cloneInto. NFC.
Diffstat (limited to 'kernel/rtlil.h')
| -rw-r--r-- | kernel/rtlil.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/kernel/rtlil.h b/kernel/rtlil.h index f751bdce4..f3dc3af68 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -1175,6 +1175,8 @@ public: RTLIL::Memory *addMemory(RTLIL::IdString name, const RTLIL::Memory *other); + RTLIL::Process *addProcess(RTLIL::IdString name, const RTLIL::Process *other); + // The add* methods create a cell and return the created cell. All signals must exist in advance. RTLIL::Cell* addNot (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = ""); |