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kernel
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rtlil.h
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Author
Age
Files
Lines
*
Bugfix in hierarchy handling of blackbox module ports
Clifford Wolf
2018-01-05
1
-1
/
+1
*
Add RTLIL::Const::is_fully_ones()
Clifford Wolf
2017-12-14
1
-0
/
+1
*
Add SigSpec::is_fully_ones()
Clifford Wolf
2017-12-14
1
-0
/
+1
*
Add src arguments to all cell creator helper functions
Clifford Wolf
2017-09-09
1
-153
/
+153
*
Merge remote-tracking branch 'upstream/master'
Jason Lowdermilk
2017-08-30
1
-0
/
+4
|
\
|
*
Add {get,set}_src_attribute() methods on RTLIL::AttrObject
Clifford Wolf
2017-08-30
1
-0
/
+4
*
|
Add support for source line tracking through synthesis phase
Jason Lowdermilk
2017-08-29
1
-18
/
+18
|
/
*
Add Const methods is_fully_zero(), is_fully_def(), and is_fully_undef()
Clifford Wolf
2017-08-18
1
-0
/
+4
*
Add "setundef -anyseq"
Clifford Wolf
2017-05-28
1
-12
/
+12
*
Add missing AndnotGate() and OrnotGate() declarations to rtlil.h
Clifford Wolf
2017-05-17
1
-13
/
+15
*
Add $_ANDNOT_ and $_ORNOT_ gates
Clifford Wolf
2017-05-17
1
-13
/
+15
*
Add $live and $fair cell types, add support for s_eventually keyword
Clifford Wolf
2017-02-25
1
-0
/
+2
*
Add $cover cell type and SVA cover() support
Clifford Wolf
2017-02-04
1
-0
/
+1
*
Remember global declarations and defines accross read_verilog calls
Clifford Wolf
2016-11-15
1
-1
/
+2
*
Added $anyseq cell type
Clifford Wolf
2016-10-14
1
-0
/
+1
*
Added $global_clock verilog syntax support for creating $ff cells
Clifford Wolf
2016-10-14
1
-1
/
+2
*
Added $ff and $_FF_ cell types
Clifford Wolf
2016-10-12
1
-0
/
+2
*
Improvements in assertpmux
Clifford Wolf
2016-09-07
1
-0
/
+3
*
Removed $predict again
Clifford Wolf
2016-08-28
1
-1
/
+0
*
Added basic support for $expect cells
Clifford Wolf
2016-07-13
1
-0
/
+2
*
A few modifications after pull request comments
Ruben Undheim
2016-06-18
1
-2
/
+1
*
Added support for SystemVerilog packages with localparam definitions
Ruben Undheim
2016-06-18
1
-0
/
+2
*
Added addBufGate module method
Clifford Wolf
2016-02-02
1
-0
/
+2
*
Meaningless coding style change
Clifford Wolf
2016-01-31
1
-1
/
+0
*
rtlil: duplicate remove2() for std::set<>
Rick Altherr
2016-01-29
1
-0
/
+2
*
rtlil: change IdString comparison operators to take references instead of copies
Rick Altherr
2016-01-29
1
-3
/
+3
*
Removed dangling ';' in rtlil.h
Clifford Wolf
2015-11-26
1
-2
/
+2
*
renamed SigSpec::to_single_sigbit() to SigSpec::as_bit(), added is_bit()
Clifford Wolf
2015-10-24
1
-1
/
+2
*
Cosmetic fix in Module::addLut()
Clifford Wolf
2015-09-18
1
-1
/
+1
*
Added $tribuf and $_TBUF_ cell types
Clifford Wolf
2015-08-16
1
-0
/
+1
*
Spell check (by Larry Doolittle)
Clifford Wolf
2015-08-14
1
-1
/
+1
*
Fixed trailing whitespaces
Clifford Wolf
2015-07-02
1
-11
/
+11
*
Added design->rename(module, new_name)
Clifford Wolf
2015-06-30
1
-0
/
+1
*
Added "rename -top new_name"
Clifford Wolf
2015-06-17
1
-0
/
+1
*
Added $eq/$neq -> $logic_not/$reduce_bool optimization
Clifford Wolf
2015-04-29
1
-0
/
+1
*
Improved attributes API and handling of "src" attributes
Clifford Wolf
2015-04-24
1
-23
/
+18
*
Added support for initialized brams
Clifford Wolf
2015-04-06
1
-1
/
+10
*
Added "dffinit", Support for initialized Xilinx DFF
Clifford Wolf
2015-04-04
1
-0
/
+1
*
Some cleanups in "clean"
Clifford Wolf
2015-02-24
1
-0
/
+8
*
Added SigSpec::has_const()
Clifford Wolf
2015-02-08
1
-0
/
+1
*
Added cell->known(), cell->input(portname), cell->output(portname)
Clifford Wolf
2015-02-07
1
-0
/
+5
*
Added "equiv_make -blacklist <file> -encfile <file>"
Clifford Wolf
2015-01-31
1
-0
/
+1
*
Synced RTLIL::unescape_id() to log_id() behavior
Clifford Wolf
2015-01-30
1
-3
/
+9
*
Added dict/pool.sort()
Clifford Wolf
2015-01-24
1
-0
/
+4
*
Added equiv_make command
Clifford Wolf
2015-01-19
1
-1
/
+2
*
Removed SigSpec::extend_xx() api
Clifford Wolf
2015-01-01
1
-1
/
+0
*
Progress in memory_bram
Clifford Wolf
2014-12-31
1
-5
/
+5
*
IdString optimization
Clifford Wolf
2014-12-31
1
-0
/
+6
*
added hashlib::mkhash_init
Clifford Wolf
2014-12-30
1
-1
/
+1
*
Added "yosys -X"
Clifford Wolf
2014-12-29
1
-0
/
+11
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