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| author | Clifford Wolf <clifford@clifford.at> | 2015-01-01 11:41:52 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2015-01-01 11:41:52 +0100 |
| commit | e62d838bd424995d2fcdc9cef1f56752905c3b4d (patch) | |
| tree | 1699bd05ec11dcf7cd38e1141eeeb58019008908 /kernel/rtlil.h | |
| parent | 327a5d42b6b396f1c210f1579d03a0806a261d84 (diff) | |
| download | yosys-e62d838bd424995d2fcdc9cef1f56752905c3b4d.tar.gz yosys-e62d838bd424995d2fcdc9cef1f56752905c3b4d.tar.bz2 yosys-e62d838bd424995d2fcdc9cef1f56752905c3b4d.zip | |
Removed SigSpec::extend_xx() api
Diffstat (limited to 'kernel/rtlil.h')
| -rw-r--r-- | kernel/rtlil.h | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 7618780b0..53ee24c22 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -651,7 +651,6 @@ public: void append(const RTLIL::SigSpec &signal); void append_bit(const RTLIL::SigBit &bit); - void extend_xx(int width, bool is_signed = false); void extend_u0(int width, bool is_signed = false); RTLIL::SigSpec repeat(int num) const; |