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* Use more ID::{A,B,Y,blackbox,whitebox}Eddie Hung2019-08-151-96/+96
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* Add YOSYS_NO_IDS_REFCNT configuration macroClifford Wolf2019-08-111-1/+3
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Use ID() in kernel/*, add simple ID:: hack (to be improved upon later)Clifford Wolf2019-08-111-578/+585
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* More improvements and cleanups in IdString subsystemClifford Wolf2019-08-111-0/+2
| | | | | | | | | - better use of "inline" keyword - deprecate "sticky" IDs feature - improve handling of empty ID - add move constructor Signed-off-by: Clifford Wolf <clifford@clifford.at>
* RTLIL::S{0,1} -> State::S{0,1}Eddie Hung2019-08-071-6/+6
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* stoi -> atoiEddie Hung2019-08-071-3/+3
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* Fix typosEddie Hung2019-08-061-2/+2
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* Use std::stoi instead of atoi(<str>.c_str())Eddie Hung2019-08-061-3/+3
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* Use IdString::begins_with()Eddie Hung2019-08-061-4/+4
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* Make liberal use of IdString.in()Eddie Hung2019-08-061-1/+1
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* Add $_NMUX_, add "abc -g cmos", add proper cmos cell costsClifford Wolf2019-08-061-0/+2
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* In RTLIL::Module::check(), check process invariants.whitequark2019-06-191-1/+28
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* Add rewrite_sigspecs2, Improve remove() wiresClifford Wolf2019-05-151-7/+22
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Minor optimization to get_attribute_boolMatthew Daiter2019-05-071-4/+8
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* Merge remote-tracking branch 'origin/master' into clifford/specifyEddie Hung2019-05-031-1/+1
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| * Fix performance bug in RTLIL::SigSpec::operator==(), fixes #970Clifford Wolf2019-04-301-1/+1
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Improve $specrule interfaceClifford Wolf2019-04-231-2/+2
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Improve $specrule interfaceClifford Wolf2019-04-231-1/+2
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Add $specrule cells for $setup/$hold/$skew specify rulesClifford Wolf2019-04-231-0/+15
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Rename T_{RISE,FALL}_AVG to T_{RISE,FALL}_TYP to better match verilog std ↵Clifford Wolf2019-04-231-2/+2
| | | | | | | | | | | | nomenclature Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Add InternalCellChecker support for $specify2 and $specify3Clifford Wolf2019-04-231-7/+21
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Add specify parserClifford Wolf2019-04-231-0/+10
|/ | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Merge pull request #905 from christian-krieg/feature/python_bindingsClifford Wolf2019-04-221-1/+97
|\ | | | | Feature/python bindings
| * Global lists in rtlil.cc are now static objectsBenedikt Tutzer2019-04-031-10/+10
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| * Merge remote-tracking branch 'origin/master' into feature/python_bindingsBenedikt Tutzer2019-03-281-3/+31
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| * | added some checks if python is enabled to make sure everything compiles if ↵Benedikt Tutzer2018-08-201-4/+2
| | | | | | | | | | | | python is disabled in the makefile
| * | Added Wrappers for:Benedikt Tutzer2018-08-131-1/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | -IdString -Const -CaseRule -SwitchRule -SyncRule -Process -SigChunk -SigBit -SigSpec With all their member functions as well as the remaining member functions for Cell, Wire, Module and Design and static functions of rtlil.h
| * | added destructors for wires and cellsBenedikt Tutzer2018-07-101-0/+14
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| * | removed debug outputBenedikt Tutzer2018-07-091-1/+0
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| * | multiple designs can now exist independent from each other. ↵Benedikt Tutzer2018-07-091-0/+55
| | | | | | | | | | | | Cells/Wires/Modules can now move to a different parent without referencing issues
* | | Add "wbflip" commandClifford Wolf2019-04-201-2/+5
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | Add "whitebox" attribute, add "read_verilog -wb"Clifford Wolf2019-04-181-3/+3
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | Add "read_ilang -lib"Clifford Wolf2019-04-051-0/+24
| |/ |/| | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Add RTLIL::Const::ext[su](), fix RTLIL::SigSpec::extend_u0 for 0-size signalsClifford Wolf2019-03-231-1/+1
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Add fmcombine passClifford Wolf2019-03-151-2/+2
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Improve determinism of IdString DB for similar scriptsClifford Wolf2019-03-111-0/+2
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Add FF support to wreduceClifford Wolf2019-02-201-0/+3
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | proc_clean: remove any empty cases if all cases use all-def compare.whitequark2018-12-231-0/+10
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* | Documentation improvements etc.Ruben Undheim2018-10-131-3/+1
| | | | | | | | | | | | | | | | | | - Mention new feature in the SystemVerilog section in the README file - Commented changes much better - Rename a few signals to make it clearer - Prevent warning for unused signals in an easier way - Add myself as copyright holder to 2 files - Fix one potential memory leak (delete 'wire' if not in modport)
* | Support for 'modports' for System Verilog interfacesRuben Undheim2018-10-121-1/+1
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* | Synthesis support for SystemVerilog interfacesRuben Undheim2018-10-121-0/+15
|/ | | | This time doing the changes mostly in AST before RTLIL generation
* Add $allconst and $allseq cell typesClifford Wolf2018-02-231-1/+21
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Bugfix in hierarchy handling of blackbox module portsClifford Wolf2018-01-051-1/+3
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add RTLIL::Const::is_fully_ones()Clifford Wolf2017-12-141-0/+11
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* Add SigSpec::is_fully_ones()Clifford Wolf2017-12-141-0/+15
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* Add src arguments to all cell creator helper functionsClifford Wolf2017-09-091-56/+91
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* Update more stuff to use get_src_attribute() and set_src_attribute()Clifford Wolf2017-09-011-1/+1
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* Merge remote-tracking branch 'upstream/master'Jason Lowdermilk2017-08-301-0/+16
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| * Add {get,set}_src_attribute() methods on RTLIL::AttrObjectClifford Wolf2017-08-301-0/+16
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* | fix indent levelJason Lowdermilk2017-08-301-2/+2
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