iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Renamed port access function on RTLIL::Cell, added param access functions	Clifford Wolf	2014-07-31	1	-82/+102
*	Added RTLIL::Monitor	Clifford Wolf	2014-07-31	1	-94/+79
*	Added module->design and cell->module, wire->module pointers	Clifford Wolf	2014-07-31	1	-0/+83
*	Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace	Clifford Wolf	2014-07-31	1	-4/+4
*	Added "techmap -map %{design-name}"	Clifford Wolf	2014-07-29	1	-0/+5
*	Added $shift and $shiftx cell types (needed for correct part select behavior)	Clifford Wolf	2014-07-29	1	-1/+4
*	Added wire->upto flag for signals such as "wire [0:7] x;"	Clifford Wolf	2014-07-28	1	-0/+2
*	Using log_assert() instead of assert()	Clifford Wolf	2014-07-28	1	-60/+59
*	Added std::initializer_list<> constructor to SigSpec	Clifford Wolf	2014-07-28	1	-0/+12
*	Added cover() to all SigSpec constructors	Clifford Wolf	2014-07-28	1	-0/+22
*	Added proper Design->addModule interface	Clifford Wolf	2014-07-27	1	-3/+36
*	Added RTLIL::SigSpec::remove_const() handling of packed SigSpecs	Clifford Wolf	2014-07-27	1	-9/+26
*	Added RTLIL::Module::wire(id) and cell(id) lookup functions	Clifford Wolf	2014-07-27	1	-0/+12
*	Refactoring: Renamed RTLIL::Design::modules to modules_	Clifford Wolf	2014-07-27	1	-9/+9
*	Added RTLIL::ObjIterator and RTLIL::ObjRange	Clifford Wolf	2014-07-27	1	-6/+23
*	Refactoring: Renamed RTLIL::Module::cells to cells_	Clifford Wolf	2014-07-27	1	-12/+12
*	Refactoring: Renamed RTLIL::Module::wires to wires_	Clifford Wolf	2014-07-27	1	-20/+20
*	Changed more code to the new RTLIL::Wire constructors	Clifford Wolf	2014-07-26	1	-1/+13
*	Changed a lot of code to the new RTLIL::Wire constructors	Clifford Wolf	2014-07-26	1	-0/+40
*	Added RTLIL::Cell::has(portname)	Clifford Wolf	2014-07-26	1	-4/+9
*	Manual fixes for new cell connections API	Clifford Wolf	2014-07-26	1	-11/+11
*	Changed users of cell->connections_ to the new API (sed command)	Clifford Wolf	2014-07-26	1	-82/+82
*	Added some missing "const" in rtlil.h	Clifford Wolf	2014-07-26	1	-5/+5
*	Added RTLIL::Module::connections()	Clifford Wolf	2014-07-26	1	-0/+5
*	Added RTLIL::Module::connect(const RTLIL::SigSig&)	Clifford Wolf	2014-07-26	1	-0/+5
*	Automatically pack SigSpec on copy/assign	Clifford Wolf	2014-07-26	1	-17/+60
*	Added new RTLIL::Cell port access methods	Clifford Wolf	2014-07-26	1	-0/+63
*	Renamed RTLIL::{Module,Cell}::connections to connections_	Clifford Wolf	2014-07-26	1	-83/+88
*	Added copy-constructor-like module->addCell(name, other) method	Clifford Wolf	2014-07-26	1	-8/+11
*	Use only module->addCell() and module->remove() to create and delete cells	Clifford Wolf	2014-07-25	1	-2/+35
*	Added RTLIL::SigSpec is_chunk()/as_chunk() API	Clifford Wolf	2014-07-25	1	-0/+17
*	Fixed typo in cover id	Clifford Wolf	2014-07-25	1	-1/+1
*	Replaced more old SigChunk programming patterns	Clifford Wolf	2014-07-24	1	-0/+17
*	Some improvements in SigSpec packing/unpacking and checking	Clifford Wolf	2014-07-24	1	-8/+29
*	Small changes regarding cover() and check() in SigSpec	Clifford Wolf	2014-07-24	1	-10/+5
*	Added support for YOSYS_COVER_FILE env variable	Clifford Wolf	2014-07-24	1	-0/+2
*	Added cover() calls to RTLIL::SigSpec methods	Clifford Wolf	2014-07-24	1	-5/+93
*	Added hashing to RTLIL::SigSpec relational and equal operators	Clifford Wolf	2014-07-23	1	-15/+64
*	Disabled RTLIL::SigSpec::check() in release builds	Clifford Wolf	2014-07-23	1	-0/+2
*	Fixed release build	Clifford Wolf	2014-07-23	1	-0/+2
*	Added RTLIL::SigSpec::repeat()	Clifford Wolf	2014-07-23	1	-0/+8
*	Removed RTLIL::SigSpec::optimize()	Clifford Wolf	2014-07-23	1	-105/+9
*	Turned RTLIL::SigSpec::optimize() to a no-op: a packed SigSpec is now always ...	Clifford Wolf	2014-07-23	1	-7/+42
*	Removed RTLIL::SigSpec::expand() method	Clifford Wolf	2014-07-23	1	-41/+0
*	Replaced RTLIL::SigSpec::operator!=() with inline version	Clifford Wolf	2014-07-23	1	-7/+0
*	Refactoring {SigSpec\|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3	Clifford Wolf	2014-07-23	1	-14/+10
*	Refactoring {SigSpec\|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 2/3	Clifford Wolf	2014-07-23	1	-16/+2
*	Refactoring {SigSpec\|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 1/3	Clifford Wolf	2014-07-23	1	-0/+32
*	Some cleanups in RTLIL::SigChunk::SigChunk(const RTLIL::Const&)	Clifford Wolf	2014-07-23	1	-4/+4
*	SigSpec refactoring: More cleanups of old SigSpec use pattern	Clifford Wolf	2014-07-22	1	-1/+11