diff options
| author | Clifford Wolf <clifford@clifford.at> | 2014-07-23 21:42:44 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-07-23 21:42:44 +0200 |
| commit | f368d792fbe6a4430dbf710b11e89cbf58439542 (patch) | |
| tree | ddcf8019b7726b6e56d35c7583eb16b0b89b35ce /kernel/rtlil.cc | |
| parent | 95ac484548d4a4550568de09343964150806042d (diff) | |
| download | yosys-f368d792fbe6a4430dbf710b11e89cbf58439542.tar.gz yosys-f368d792fbe6a4430dbf710b11e89cbf58439542.tar.bz2 yosys-f368d792fbe6a4430dbf710b11e89cbf58439542.zip | |
Disabled RTLIL::SigSpec::check() in release builds
Diffstat (limited to 'kernel/rtlil.cc')
| -rw-r--r-- | kernel/rtlil.cc | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 7d630b352..b0958bd0d 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -1808,6 +1808,7 @@ RTLIL::SigSpec RTLIL::SigSpec::repeat(int num) const void RTLIL::SigSpec::check() const { +#ifndef NDEBUG if (packed()) { int w = 0; @@ -1836,6 +1837,7 @@ void RTLIL::SigSpec::check() const assert(width_ == SIZE(bits_)); assert(chunks_.empty()); } +#endif } bool RTLIL::SigSpec::operator <(const RTLIL::SigSpec &other) const |