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author | Clifford Wolf <clifford@clifford.at> | 2014-07-27 11:03:56 +0200 |
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committer | Clifford Wolf <clifford@clifford.at> | 2014-07-27 11:18:31 +0200 |
commit | 675cb93da9e67f5c2fe8a3760de5893176ea906d (patch) | |
tree | 0c17ca0e96bcfebb82be4e8cfe4b15562c5ac541 /kernel/rtlil.cc | |
parent | 0bd8fafbd2f36f59327289e52abf962c166dab8b (diff) | |
download | yosys-675cb93da9e67f5c2fe8a3760de5893176ea906d.tar.gz yosys-675cb93da9e67f5c2fe8a3760de5893176ea906d.tar.bz2 yosys-675cb93da9e67f5c2fe8a3760de5893176ea906d.zip |
Added RTLIL::Module::wire(id) and cell(id) lookup functions
Diffstat (limited to 'kernel/rtlil.cc')
-rw-r--r-- | kernel/rtlil.cc | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 5709875ec..db85f9e3d 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -274,6 +274,16 @@ bool RTLIL::Design::selected_member(RTLIL::IdString mod_name, RTLIL::IdString me return selection_stack.back().selected_member(mod_name, memb_name); } +bool RTLIL::Design::selected_module(RTLIL::Module *mod) const +{ + return selected_module(mod->name); +} + +bool RTLIL::Design::selected_whole_module(RTLIL::Module *mod) const +{ + return selected_whole_module(mod->name); +} + RTLIL::Module::Module() { refcount_wires_ = 0; @@ -1502,6 +1512,7 @@ RTLIL::SigChunk::SigChunk(const RTLIL::Const &value) RTLIL::SigChunk::SigChunk(RTLIL::Wire *wire) { + log_assert(wire != nullptr); this->wire = wire; this->width = wire->width; this->offset = 0; @@ -1509,6 +1520,7 @@ RTLIL::SigChunk::SigChunk(RTLIL::Wire *wire) RTLIL::SigChunk::SigChunk(RTLIL::Wire *wire, int offset, int width) { + log_assert(wire != nullptr); this->wire = wire; this->width = width; this->offset = offset; |