| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| ... | |
| * | Added $macc cell type | Clifford Wolf | 2014-09-06 | 1 | -1/+13 |
| * | Removed $bu0 cell type | Clifford Wolf | 2014-09-04 | 1 | -2/+1 |
| * | Create a default selection stack in RTLIL::Design::Design() | Clifford Wolf | 2014-09-02 | 1 | -0/+1 |
| * | Using std::vector<RTLIL::State> instead of RTLIL::Const for RTLIL::SigChunk::... | Clifford Wolf | 2014-09-01 | 1 | -33/+29 |
| * | Added $lut support in test_cell, techmap, satgen | Clifford Wolf | 2014-08-31 | 1 | -3/+7 |
| * | Added design->scratchpad | Clifford Wolf | 2014-08-30 | 1 | -0/+61 |
| * | Added $alu cell type | Clifford Wolf | 2014-08-30 | 1 | -0/+14 |
| * | Fixed module->addPmux() | Clifford Wolf | 2014-08-30 | 1 | -1/+0 |
| * | Added is_signed argument to SigSpec.as_int() and Const.as_int() | Clifford Wolf | 2014-08-24 | 1 | -4/+7 |
| * | Changed backend-api from FILE to std::ostream | Clifford Wolf | 2014-08-23 | 1 | -8/+3 |
| * | Added emscripten (emcc) support to build system and some build fixes | Clifford Wolf | 2014-08-22 | 1 | -0/+4 |
| * | Added mod->addGate() methods for new gate types | Clifford Wolf | 2014-08-19 | 1 | -53/+76 |
| * | Improved sig.remove2() performance | Clifford Wolf | 2014-08-17 | 1 | -2/+11 |
| * | Added module->uniquify() | Clifford Wolf | 2014-08-16 | 1 | -0/+22 |
| * | Added additional gate types: $_NAND_ $_NOR_ $_XNOR_ $_AOI3_ $_OAI3_ $_AOI4_ $... | Clifford Wolf | 2014-08-16 | 1 | -5/+12 |
| * | Renamed $lut ports to follow A-Y naming scheme | Clifford Wolf | 2014-08-15 | 1 | -4/+4 |
| * | Renamed $_INV_ cell type to $_NOT_ | Clifford Wolf | 2014-08-15 | 1 | -2/+2 |
| * | Added RTLIL::SigSpec::to_sigbit_map() | Clifford Wolf | 2014-08-14 | 1 | -0/+16 |
| * | Added sig.{replace,remove,extract} variants for std::{map,set} pattern | Clifford Wolf | 2014-08-14 | 1 | -24/+53 |
| * | Added module->ports | Clifford Wolf | 2014-08-14 | 1 | -1/+9 |
| * | Refactoring of CellType class | Clifford Wolf | 2014-08-14 | 1 | -10/+6 |
| * | RIP $safe_pmux | Clifford Wolf | 2014-08-14 | 1 | -4/+3 |
| * | Added support for truncating of wires to wreduce pass | Clifford Wolf | 2014-08-05 | 1 | -0/+30 |
| * | Bugfix in "techmap -extern" | Clifford Wolf | 2014-08-02 | 1 | -10/+16 |
| * | Removed at() method from RTLIL::IdString | Clifford Wolf | 2014-08-02 | 1 | -2/+2 |
| * | No implicit conversion from IdString to anything else | Clifford Wolf | 2014-08-02 | 1 | -14/+14 |
| * | Improvements in new RTLIL::IdString implementation | Clifford Wolf | 2014-08-02 | 1 | -2/+2 |
| * | Implemented new reference counting RTLIL::IdString | Clifford Wolf | 2014-08-02 | 1 | -2/+6 |
| * | More cleanups related to RTLIL::IdString usage | Clifford Wolf | 2014-08-02 | 1 | -1/+1 |
| * | Added ModIndex helper class, some changes to RTLIL::Monitor | Clifford Wolf | 2014-08-01 | 1 | -13/+23 |
| * | Packed SigBit::data and SigBit::offset in a union | Clifford Wolf | 2014-08-01 | 1 | -1/+3 |
| * | Renamed port access function on RTLIL::Cell, added param access functions | Clifford Wolf | 2014-07-31 | 1 | -82/+102 |
| * | Added RTLIL::Monitor | Clifford Wolf | 2014-07-31 | 1 | -94/+79 |
| * | Added module->design and cell->module, wire->module pointers | Clifford Wolf | 2014-07-31 | 1 | -0/+83 |
| * | Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace | Clifford Wolf | 2014-07-31 | 1 | -4/+4 |
| * | Added "techmap -map %{design-name}" | Clifford Wolf | 2014-07-29 | 1 | -0/+5 |
| * | Added $shift and $shiftx cell types (needed for correct part select behavior) | Clifford Wolf | 2014-07-29 | 1 | -1/+4 |
| * | Added wire->upto flag for signals such as "wire [0:7] x;" | Clifford Wolf | 2014-07-28 | 1 | -0/+2 |
| * | Using log_assert() instead of assert() | Clifford Wolf | 2014-07-28 | 1 | -60/+59 |
| * | Added std::initializer_list<> constructor to SigSpec | Clifford Wolf | 2014-07-28 | 1 | -0/+12 |
| * | Added cover() to all SigSpec constructors | Clifford Wolf | 2014-07-28 | 1 | -0/+22 |
| * | Added proper Design->addModule interface | Clifford Wolf | 2014-07-27 | 1 | -3/+36 |
| * | Added RTLIL::SigSpec::remove_const() handling of packed SigSpecs | Clifford Wolf | 2014-07-27 | 1 | -9/+26 |
| * | Added RTLIL::Module::wire(id) and cell(id) lookup functions | Clifford Wolf | 2014-07-27 | 1 | -0/+12 |
| * | Refactoring: Renamed RTLIL::Design::modules to modules_ | Clifford Wolf | 2014-07-27 | 1 | -9/+9 |
| * | Added RTLIL::ObjIterator and RTLIL::ObjRange | Clifford Wolf | 2014-07-27 | 1 | -6/+23 |
| * | Refactoring: Renamed RTLIL::Module::cells to cells_ | Clifford Wolf | 2014-07-27 | 1 | -12/+12 |
| * | Refactoring: Renamed RTLIL::Module::wires to wires_ | Clifford Wolf | 2014-07-27 | 1 | -20/+20 |
| * | Changed more code to the new RTLIL::Wire constructors | Clifford Wolf | 2014-07-26 | 1 | -1/+13 |
| * | Changed a lot of code to the new RTLIL::Wire constructors | Clifford Wolf | 2014-07-26 | 1 | -0/+40 |
