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sv: Fix memories of typedefs
David Shah
2019-10-03
1
-1
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+1
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sv: Add %expect
David Shah
2019-10-03
1
-0
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+1
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sv: Add support for memories of a typedef
David Shah
2019-10-03
1
-6
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+20
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sv: Add support for memory typedefs
David Shah
2019-10-03
2
-3
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+34
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sv: Fix typedefs in packages
David Shah
2019-10-03
1
-4
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+10
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sv: Fix typedef parameters
David Shah
2019-10-03
2
-6
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+48
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sv: Switch parser to glr, prep for typedef
David Shah
2019-10-03
5
-11
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+89
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Merge remote-tracking branch 'origin/master' into xaig_dff
Eddie Hung
2019-10-08
1
-2
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+6
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Merge pull request #1437 from YosysHQ/eddie/abc_to_abc9
Eddie Hung
2019-10-08
1
-4
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+4
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Fixes for MSVC build
Miodrag Milanovic
2019-10-04
1
-2
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+6
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Fix merge issues
Eddie Hung
2019-10-04
1
-1
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+1
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Merge remote-tracking branch 'origin/eddie/abc_to_abc9' into xaig_dff
Eddie Hung
2019-10-04
1
-4
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+4
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Rename abc_* names/attributes to more precisely be abc9_*
Eddie Hung
2019-10-04
1
-4
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+4
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Merge remote-tracking branch 'origin/master' into xaig_dff
Eddie Hung
2019-10-03
3
-35
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+61
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Merge pull request #1419 from YosysHQ/eddie/lazy_derive
Clifford Wolf
2019-10-03
2
-35
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+59
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Fix for svinterfaces
Eddie Hung
2019-09-30
1
-2
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+8
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module->derive() to be lazy and not touch ast if already derived
Eddie Hung
2019-09-30
2
-33
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+51
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Define environ, fixes #1424
Miodrag Milanovic
2019-10-01
1
-0
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+2
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Cleanup $currQ from aigerparse
Eddie Hung
2019-09-30
1
-2
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+0
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Merge remote-tracking branch 'origin/master' into xaig_dff
Eddie Hung
2019-09-30
3
-2
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+597
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Merge pull request #1406 from whitequark/connect_rpc
whitequark
2019-09-30
2
-0
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+591
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rpc: new frontend.
whitequark
2019-09-30
2
-0
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+591
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Merge pull request #1416 from YosysHQ/mmicko/frontend_binary_in
Miodrag Milanović
2019-09-30
1
-2
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+6
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Fix reading aig files on windows
Miodrag Milanovic
2019-09-29
1
-1
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+5
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Open aig frontend as binary file
Miodrag Milanovic
2019-09-29
1
-1
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+1
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Merge remote-tracking branch 'origin/master' into xaig_dff
Eddie Hung
2019-09-29
1
-2
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+2
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Force $inout.out ports to begin with '$' to indicate internal
Eddie Hung
2019-09-23
1
-2
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+2
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Big rework; flop info now mostly in cells_sim.v
Eddie Hung
2019-09-28
1
-6
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+13
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Merge remote-tracking branch 'origin/master' into xaig_dff
Eddie Hung
2019-09-27
5
-35
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+73
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Fix handling of read_verilog config in AstModule::reprocess_module(), fixes #...
Clifford Wolf
2019-09-20
2
-18
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+30
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Merge pull request #1355 from YosysHQ/eddie/peepopt_dffmuxext
Eddie Hung
2019-09-18
1
-1
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+1
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Revert "parse_xaiger() to do "clean -purge""
Eddie Hung
2019-09-04
1
-1
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+1
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Fix handling of range selects on loop variables, fixes #1372
Clifford Wolf
2019-09-16
1
-2
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+9
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Fix handling of z_digit "?" and fix optimization of cmp with "z"
Clifford Wolf
2019-09-13
1
-5
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+1
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Fix lexing of integer literals without radix
Clifford Wolf
2019-09-13
1
-1
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+1
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Fix lexing of integer literals, fixes #1364
Clifford Wolf
2019-09-12
2
-3
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+3
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Merge pull request #1312 from YosysHQ/xaig_arrival
Eddie Hung
2019-09-05
1
-14
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+25
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Merge remote-tracking branch 'origin/master' into xaig_arrival
Eddie Hung
2019-09-04
1
-0
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+7
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Merge remote-tracking branch 'origin/master' into xaig_arrival
Eddie Hung
2019-08-30
1
-1
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+1
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Merge remote-tracking branch 'origin/master' into xaig_arrival
Eddie Hung
2019-08-23
1
-0
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+5
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Merge pull request #1350 from YosysHQ/clifford/fixsby59
Clifford Wolf
2019-09-05
1
-7
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+18
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Properly construct $live and $fair cells from "if (...) assume/assert (s_even...
Clifford Wolf
2019-09-02
1
-7
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+18
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Merge remote-tracking branch 'origin/master' into eddie/deferred_top
Eddie Hung
2019-09-03
1
-1
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+1
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parse_xaiger() to do "clean -purge"
Eddie Hung
2019-08-29
1
-1
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+1
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Remove newline
Eddie Hung
2019-08-29
1
-1
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+0
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Restore non-deferred code, deferred case to ignore non constant attr
Eddie Hung
2019-08-29
1
-5
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+12
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read_verilog -defer should still populate module attributes
Eddie Hung
2019-08-28
1
-5
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+6
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Do not propagate mem2reg attribute through to result
Eddie Hung
2019-08-22
1
-1
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+2
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mem2reg to preserve user attributes and src
Eddie Hung
2019-08-21
1
-0
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+4
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Revert "Remove sequential extension"
Eddie Hung
2019-08-20
1
-2
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+33
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