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| author | Eddie Hung <eddie@fpgeh.com> | 2019-09-23 21:58:04 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-09-23 21:58:04 -0700 |
| commit | c340fbfab23c582103402bbd812d9bca4510dc41 (patch) | |
| tree | 6aef6aa91610b8247b97ad9eb7fc0308bc294915 /frontends | |
| parent | 11ac37733d436d5c0217fa6da029d620ec3da1b3 (diff) | |
| download | yosys-c340fbfab23c582103402bbd812d9bca4510dc41.tar.gz yosys-c340fbfab23c582103402bbd812d9bca4510dc41.tar.bz2 yosys-c340fbfab23c582103402bbd812d9bca4510dc41.zip | |
Force $inout.out ports to begin with '$' to indicate internal
Diffstat (limited to 'frontends')
| -rw-r--r-- | frontends/aiger/aigerparse.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc index e8ee487e5..986d34fb3 100644 --- a/frontends/aiger/aigerparse.cc +++ b/frontends/aiger/aigerparse.cc @@ -868,7 +868,7 @@ void AigerReader::post_process() if (!existing) { if (escaped_s.ends_with("$inout.out")) { wire->port_output = false; - RTLIL::Wire *in_wire = module->wire(escaped_s.substr(0, escaped_s.size()-10)); + RTLIL::Wire *in_wire = module->wire(escaped_s.substr(1, escaped_s.size()-11)); log_assert(in_wire); log_assert(in_wire->port_input && !in_wire->port_output); in_wire->port_output = true; @@ -889,7 +889,7 @@ void AigerReader::post_process() if (!existing) { if (escaped_s.ends_with("$inout.out")) { wire->port_output = false; - RTLIL::Wire *in_wire = module->wire(stringf("%s[%d]", escaped_s.substr(0, escaped_s.size()-10).c_str(), index)); + RTLIL::Wire *in_wire = module->wire(stringf("%s[%d]", escaped_s.substr(1, escaped_s.size()-11).c_str(), index)); log_assert(in_wire); log_assert(in_wire->port_input && !in_wire->port_output); in_wire->port_output = true; |