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author | Eddie Hung <eddie@fpgeh.com> | 2019-09-03 10:49:21 -0700 |
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committer | Eddie Hung <eddie@fpgeh.com> | 2019-09-03 10:49:21 -0700 |
commit | d6a84a78a7ca70e567bc1b0665751daf0e44f4ae (patch) | |
tree | 131ecdaa9713cdcf31f5e5fe11aa86e877ac5103 /frontends | |
parent | 67587bad7fb1adf14ca9598bb1a01d0ffda6a018 (diff) | |
parent | 58af64b63a3a253ab08b1410422677deac5c6618 (diff) | |
download | yosys-d6a84a78a7ca70e567bc1b0665751daf0e44f4ae.tar.gz yosys-d6a84a78a7ca70e567bc1b0665751daf0e44f4ae.tar.bz2 yosys-d6a84a78a7ca70e567bc1b0665751daf0e44f4ae.zip |
Merge remote-tracking branch 'origin/master' into eddie/deferred_top
Diffstat (limited to 'frontends')
-rw-r--r-- | frontends/aiger/aigerparse.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc index 06522939f..2e1fb8fad 100644 --- a/frontends/aiger/aigerparse.cc +++ b/frontends/aiger/aigerparse.cc @@ -974,7 +974,7 @@ void AigerReader::post_process() // operate (and run checks on) this one module RTLIL::Design *mapped_design = new RTLIL::Design; mapped_design->add(module); - Pass::call(mapped_design, "clean"); + Pass::call(mapped_design, "clean -purge"); mapped_design->modules_.erase(module->name); delete mapped_design; |