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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-28 19:59:09 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-28 19:59:09 -0700 |
| commit | 34ae29295db53289e786c0279ed00474cf0294d3 (patch) | |
| tree | aa4d36bdbfe9ff8ab6d1ceee8591f72179068d58 /frontends | |
| parent | 1fdb3fc98cdbd7126f07778397e3c334f45945df (diff) | |
| download | yosys-34ae29295db53289e786c0279ed00474cf0294d3.tar.gz yosys-34ae29295db53289e786c0279ed00474cf0294d3.tar.bz2 yosys-34ae29295db53289e786c0279ed00474cf0294d3.zip | |
read_verilog -defer should still populate module attributes
Diffstat (limited to 'frontends')
| -rw-r--r-- | frontends/ast/ast.cc | 11 |
1 files changed, 6 insertions, 5 deletions
diff --git a/frontends/ast/ast.cc b/frontends/ast/ast.cc index 82283fb5b..6a91c418b 100644 --- a/frontends/ast/ast.cc +++ b/frontends/ast/ast.cc @@ -1073,11 +1073,6 @@ static AstModule* process_module(AstNode *ast, bool defer, AstNode *original_ast ignoreThisSignalsInInitial = RTLIL::SigSpec(); - for (auto &attr : ast->attributes) { - if (attr.second->type != AST_CONSTANT) - log_file_error(ast->filename, ast->linenum, "Attribute `%s' with non-constant value!\n", attr.first.c_str()); - current_module->attributes[attr.first] = attr.second->asAttrConst(); - } for (size_t i = 0; i < ast->children.size(); i++) { AstNode *node = ast->children[i]; if (node->type == AST_WIRE || node->type == AST_MEMORY) @@ -1100,6 +1095,12 @@ static AstModule* process_module(AstNode *ast, bool defer, AstNode *original_ast ignoreThisSignalsInInitial = RTLIL::SigSpec(); } + for (auto &attr : ast->attributes) { + if (attr.second->type != AST_CONSTANT) + log_file_error(ast->filename, ast->linenum, "Attribute `%s' with non-constant value!\n", attr.first.c_str()); + current_module->attributes[attr.first] = attr.second->asAttrConst(); + } + if (ast->type == AST_INTERFACE) current_module->set_bool_attribute("\\is_interface"); current_module->ast = ast_before_simplify; |