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| author | Eddie Hung <eddie@fpgeh.com> | 2019-10-04 16:58:55 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-10-04 16:58:55 -0700 |
| commit | 7a45cd58566310f623bd567a393beb8a734ebf60 (patch) | |
| tree | 3f97ec0e46c9f01db76e3f239140ce828b14b453 /frontends | |
| parent | 549d6ea467bddba24cc0ee43597b5ab62eb476e7 (diff) | |
| parent | aae2b9fd9c8dc915fadacc24962436dd7aedff36 (diff) | |
| download | yosys-7a45cd58566310f623bd567a393beb8a734ebf60.tar.gz yosys-7a45cd58566310f623bd567a393beb8a734ebf60.tar.bz2 yosys-7a45cd58566310f623bd567a393beb8a734ebf60.zip | |
Merge remote-tracking branch 'origin/eddie/abc_to_abc9' into xaig_dff
Diffstat (limited to 'frontends')
| -rw-r--r-- | frontends/aiger/aigerparse.cc | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc index 594bf60ce..77a49c34f 100644 --- a/frontends/aiger/aigerparse.cc +++ b/frontends/aiger/aigerparse.cc @@ -747,22 +747,22 @@ void AigerReader::post_process() flops.insert(cell->type); is_flop = true; } - auto it = box_module->attributes.find("\\abc_carry"); + auto it = box_module->attributes.find("\\abc9_carry"); if (it != box_module->attributes.end()) { RTLIL::Wire *carry_in = nullptr, *carry_out = nullptr; auto carry_in_out = it->second.decode_string(); auto pos = carry_in_out.find(','); if (pos == std::string::npos) - log_error("'abc_carry' attribute on module '%s' does not contain ','.\n", log_id(cell->type)); + log_error("'abc9_carry' attribute on module '%s' does not contain ','.\n", log_id(cell->type)); auto carry_in_name = RTLIL::escape_id(carry_in_out.substr(0, pos)); carry_in = box_module->wire(carry_in_name); if (!carry_in || !carry_in->port_input) - log_error("'abc_carry' on module '%s' contains '%s' which does not exist or is not an input port.\n", log_id(cell->type), carry_in_name.c_str()); + log_error("'abc9_carry' on module '%s' contains '%s' which does not exist or is not an input port.\n", log_id(cell->type), carry_in_name.c_str()); auto carry_out_name = RTLIL::escape_id(carry_in_out.substr(pos+1)); carry_out = box_module->wire(carry_out_name); if (!carry_out || !carry_out->port_output) - log_error("'abc_carry' on module '%s' contains '%s' which does not exist or is not an output port.\n", log_id(cell->type), carry_out_name.c_str()); + log_error("'abc9_carry' on module '%s' contains '%s' which does not exist or is not an output port.\n", log_id(cell->type), carry_out_name.c_str()); auto &ports = box_module->ports; for (auto jt = ports.begin(); jt != ports.end(); ) { |