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authorEddie Hung <eddie@fpgeh.com>2019-09-18 12:40:08 -0700
committerGitHub <noreply@github.com>2019-09-18 12:40:08 -0700
commitb66c99ece042e2dcda86ffa784e927eb910168a1 (patch)
tree5d688bf80ea58fa95f97f61bab06b112937a5707 /frontends
parent3ec28ec53a4350d041cd24a4fa9b03e985d20d95 (diff)
parentf492567c872c1f6bc864fe0a3d86021558f8101e (diff)
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Merge pull request #1355 from YosysHQ/eddie/peepopt_dffmuxext
peepopt_dffmux -- bit optimisations for word level $dff + (enable/reset) $mux cells
Diffstat (limited to 'frontends')
-rw-r--r--frontends/aiger/aigerparse.cc2
1 files changed, 1 insertions, 1 deletions
diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc
index a8d5abc1e..e8ee487e5 100644
--- a/frontends/aiger/aigerparse.cc
+++ b/frontends/aiger/aigerparse.cc
@@ -985,7 +985,7 @@ void AigerReader::post_process()
// operate (and run checks on) this one module
RTLIL::Design *mapped_design = new RTLIL::Design;
mapped_design->add(module);
- Pass::call(mapped_design, "clean -purge");
+ Pass::call(mapped_design, "clean");
mapped_design->modules_.erase(module->name);
delete mapped_design;