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Author
Age
Files
Lines
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sv: Improve handling of wildcard port connections
David Shah
2020-02-02
2
-4
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+6
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hierarchy: Resolve SV wildcard port connections
David Shah
2020-02-02
1
-1
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+1
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sv: Add lexing and parsing of .* (wildcard port conns)
David Shah
2020-02-02
2
-1
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+6
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Merge pull request #1647 from YosysHQ/dave/sprintf
David Shah
2020-02-02
2
-93
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+110
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ast: Add support for $sformatf system function
David Shah
2020-01-19
2
-93
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+110
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Merge pull request #1667 from YosysHQ/clifford/verificnand
Claire Wolf
2020-01-30
1
-0
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+8
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Add Verific support for OPER_REDUCE_NAND
Claire Wolf
2020-01-30
1
-0
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+8
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Merge pull request #1503 from YosysHQ/eddie/verific_help
Claire Wolf
2020-01-30
1
-8
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+8
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Merge remote-tracking branch 'origin/master' into eddie/verific_help
Eddie Hung
2020-01-27
11
-229
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+347
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verific: no help() when no YOSYS_ENABLE_VERIFIC
Eddie Hung
2020-01-27
1
-4
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+1
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Oops
Eddie Hung
2019-11-19
1
-1
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+1
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Print help message for verific pass
Eddie Hung
2019-11-19
1
-9
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+12
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Merge pull request #1654 from YosysHQ/eddie/sby_fix69
Claire Wolf
2020-01-30
1
-0
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+6
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verific: also unflatten for 'hierarchy' flow as per @cliffordwolf
Eddie Hung
2020-01-27
1
-0
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+3
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verific: unflatten struct ports
Eddie Hung
2020-01-24
1
-0
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+3
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Add and use SigSpec::reverse()
Eddie Hung
2020-01-28
1
-3
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+3
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xilinx/ice40/ecp5: undo permuting LUT masks in lut_map
Eddie Hung
2020-01-27
1
-2
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+4
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read_aiger: set abc9_box_seq attr
Eddie Hung
2020-01-24
1
-0
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+1
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read_aiger: also parse abc9_mergeability
Eddie Hung
2020-01-22
2
-2
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+6
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read_aiger: discard LUT inputs with nodeID == 0; not < 2
Eddie Hung
2020-01-21
1
-1
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+1
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read_aiger: ignore constant inputs on LUTs
Eddie Hung
2020-01-21
1
-3
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+7
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Merge remote-tracking branch 'origin/master' into eddie/abc9_refactor
Eddie Hung
2020-01-15
1
-2
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+2
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read_aiger: $lut prefix in front
Eddie Hung
2020-01-15
1
-2
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+2
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Merge remote-tracking branch 'origin/master' into eddie/abc9_refactor
Eddie Hung
2020-01-14
2
-13
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+17
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read_aiger: also rename "$0"
Eddie Hung
2020-01-14
1
-2
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+2
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read_aiger: uniquify wires with $aiger<autoidx> prefix
Eddie Hung
2020-01-13
2
-9
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+13
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read_aiger: make $and/$not/$lut the prefix not suffix
Eddie Hung
2020-01-13
1
-5
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+5
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abc9: break SCC by setting (* keep *) on output wires
Eddie Hung
2020-01-13
1
-1
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+3
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read_aiger: more accurate debug message
Eddie Hung
2020-01-09
1
-2
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+4
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read_aiger: do not double-count outputs for flops
Eddie Hung
2020-01-09
1
-6
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+0
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Merge remote-tracking branch 'origin/master' into eddie/abc9_refactor
Eddie Hung
2020-01-07
1
-5
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+20
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read_aiger: consistency between ascii and binary; also name latches
Eddie Hung
2020-01-07
1
-3
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+9
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read_aiger: connect identical signals together
Eddie Hung
2020-01-07
1
-0
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+1
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read_aiger: cope with latches and POs with same name
Eddie Hung
2020-01-07
1
-2
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+12
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read_aiger: default -clk_name to be empty
Eddie Hung
2020-01-07
1
-1
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+1
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read_aiger fixes
Eddie Hung
2020-01-07
1
-5
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+5
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read_aiger: do not process box connections, work standalone
Eddie Hung
2020-01-07
1
-115
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+46
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read_aiger: consistency between ascii and binary
Eddie Hung
2020-01-07
1
-13
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+7
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read_aiger: add -xaiger option
Eddie Hung
2020-01-06
1
-7
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+17
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parse_xaiger to not take box_lookup
Eddie Hung
2019-12-31
2
-18
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+20
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parse_xaiger to reorder ports too
Eddie Hung
2019-12-31
1
-41
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+26
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Merge remote-tracking branch 'origin/master' into xaig_dff
Eddie Hung
2019-12-20
1
-0
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+16
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Merge pull request #1569 from YosysHQ/eddie/fix_1531
Eddie Hung
2019-12-19
1
-0
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+16
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Stray log_dump
Eddie Hung
2019-12-11
1
-1
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+0
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Preserve size of $genval$-s in for loops
Eddie Hung
2019-12-11
1
-0
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+17
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Merge remote-tracking branch 'origin/master' into xaig_dff
Eddie Hung
2019-12-19
4
-7
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+28
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Send people to symbioticeda.com instead of verific.com
Clifford Wolf
2019-12-18
2
-5
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+26
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Fixed some missing "verilog_" in documentation
Rodrigo Alejandro Melo
2019-12-13
2
-2
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+2
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aiger frontend to user shorter, $-prefixed, names
Eddie Hung
2019-12-17
1
-14
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+14
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Cleanup xaiger, remove unnecessary complexity with inout
Eddie Hung
2019-12-17
1
-23
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+4
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