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authorEddie Hung <eddie@fpgeh.com>2020-01-06 12:43:29 -0800
committerEddie Hung <eddie@fpgeh.com>2020-01-06 12:43:29 -0800
commit83616e7866138a91d0b4f60b02e32877c1a34ac1 (patch)
treec3f432558aadeb94962f4df72b5b65078ffb9c8c /frontends
parentb70e87137d6409b7b05d5d032617ee5d7048a86d (diff)
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read_aiger: add -xaiger option
Diffstat (limited to 'frontends')
-rw-r--r--frontends/aiger/aigerparse.cc24
1 files changed, 17 insertions, 7 deletions
diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc
index f030933ec..d6efdaafe 100644
--- a/frontends/aiger/aigerparse.cc
+++ b/frontends/aiger/aigerparse.cc
@@ -1000,18 +1000,21 @@ struct AigerFrontend : public Frontend {
log("Load module from an AIGER file into the current design.\n");
log("\n");
log(" -module_name <module_name>\n");
- log(" Name of module to be created (default: <filename>)\n");
+ log(" name of module to be created (default: <filename>)\n");
log("\n");
log(" -clk_name <wire_name>\n");
- log(" If specified, AIGER latches to be transformed into $_DFF_P_ cells\n");
- log(" clocked by wire of this name. Otherwise, $_FF_ cells will be used.\n");
+ log(" if specified, AIGER latches to be transformed into $_DFF_P_ cells\n");
+ log(" clocked by wire of this name. otherwise, $_FF_ cells will be used\n");
log("\n");
log(" -map <filename>\n");
log(" read file with port and latch symbols\n");
log("\n");
log(" -wideports\n");
- log(" Merge ports that match the pattern 'name[int]' into a single\n");
- log(" multi-bit port 'name'.\n");
+ log(" merge ports that match the pattern 'name[int]' into a single\n");
+ log(" multi-bit port 'name'\n");
+ log("\n");
+ log(" -xaiger\n");
+ log(" read XAIGER extensions\n");
log("\n");
}
void execute(std::istream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
@@ -1021,7 +1024,7 @@ struct AigerFrontend : public Frontend {
RTLIL::IdString clk_name = "\\clk";
RTLIL::IdString module_name;
std::string map_filename;
- bool wideports = false;
+ bool wideports = false, xaiger = false;
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++) {
@@ -1042,6 +1045,10 @@ struct AigerFrontend : public Frontend {
wideports = true;
continue;
}
+ if (arg == "-xaiger") {
+ xaiger = true;
+ continue;
+ }
break;
}
extra_args(f, filename, args, argidx, true);
@@ -1061,7 +1068,10 @@ struct AigerFrontend : public Frontend {
}
AigerReader reader(design, *f, module_name, clk_name, map_filename, wideports);
- reader.parse_aiger();
+ if (xaiger)
+ reader.parse_xaiger();
+ else
+ reader.parse_aiger();
}
} AigerFrontend;