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| author | Eddie Hung <eddie@fpgeh.com> | 2020-01-21 12:29:07 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-01-27 13:30:27 -0800 |
| commit | ce6a690d27f3ce3b637f1d9be42b1efd744500d2 (patch) | |
| tree | a369f2a8eef142f5dab828778cfa7eab8b20e363 /frontends | |
| parent | 48f3f5213eb25237b2e856827a45a9f2baefebe9 (diff) | |
| download | yosys-ce6a690d27f3ce3b637f1d9be42b1efd744500d2.tar.gz yosys-ce6a690d27f3ce3b637f1d9be42b1efd744500d2.tar.bz2 yosys-ce6a690d27f3ce3b637f1d9be42b1efd744500d2.zip | |
xilinx/ice40/ecp5: undo permuting LUT masks in lut_map
Now done in read_aiger
Diffstat (limited to 'frontends')
| -rw-r--r-- | frontends/aiger/aigerparse.cc | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc index 418fd722c..f92a11c6d 100644 --- a/frontends/aiger/aigerparse.cc +++ b/frontends/aiger/aigerparse.cc @@ -410,7 +410,7 @@ void AigerReader::parse_xaiger() RTLIL::Wire *output_sig = module->wire(stringf("$aiger%d$%d", aiger_autoidx, rootNodeID)); log_assert(output_sig); uint32_t nodeID; - RTLIL::SigSpec input_sig; + std::vector<SigBit> input_bits; for (unsigned j = 0; j < cutLeavesM; ++j) { nodeID = parse_xaiger_literal(f); log_debug2("\t%u\n", nodeID); @@ -420,8 +420,10 @@ void AigerReader::parse_xaiger() } RTLIL::Wire *wire = module->wire(stringf("$aiger%d$%d", aiger_autoidx, nodeID)); log_assert(wire); - input_sig.append(wire); + input_bits.push_back(wire); } + // Reverse input order as fastest input is returned first + RTLIL::SigSpec input_sig(std::vector<SigBit>(input_bits.rbegin(), input_bits.rend())); // TODO: Compute LUT mask from AIG in less than O(2 ** input_sig.size()) ce.clear(); ce.compute_deps(output_sig, input_sig.to_sigbit_pool()); |